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Commit | Line | Data |
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1 | page 200\r | |
2 | \r | |
3 | ; Simple polling drivers for ASCI0 and ASCI1\r | |
4 | \r | |
5 | extrn ioiniml\r | |
6 | \r | |
7 | global as0init\r | |
8 | global as0ista,as0inp\r | |
9 | global as0osta,as0out\r | |
10 | global as1init\r | |
11 | global as1ista,as1inp\r | |
12 | global as1osta,as1out\r | |
13 | \r | |
14 | \r | |
15 | extrn f_cpu,add_hla,div32_r\r | |
16 | extrn @ctbl\r | |
17 | \r | |
18 | include config.inc\r | |
19 | include z180reg.inc\r | |
20 | \r | |
21 | \r | |
22 | ;--------------------------------------------------------------\r | |
23 | ; TC = (f PHI /(2*baudrate*Clock_mode)) - 2\r | |
24 | ;\r | |
25 | ; Clock_mode == 16\r | |
26 | ; TC = (f PHI / (32 * baudrate)) - 2\r | |
27 | ;\r | |
28 | ; br150 = baudrate/150\r | |
29 | ; TC = (f PHI / (32 * 150 * br150)) - 2\r | |
30 | ; TC = (f PHI / (32 * 150 * br150)) - 2\r | |
31 | \r | |
32 | \r | |
33 | ;\r | |
34 | ; Init Serial I/O for console input and output (ASCI1)\r | |
35 | ;\r | |
36 | \r | |
37 | dseg\r | |
38 | \r | |
39 | as0init:\r | |
40 | ld hl,initab0\r | |
41 | jr as_init\r | |
42 | as1init:\r | |
43 | ld hl,initab1\r | |
44 | as_init:\r | |
45 | push hl\r | |
46 | \r | |
47 | ld c,8 ;\r | |
48 | mlt bc ;\r | |
49 | ld hl,@ctbl+7 ;get baudrate index\r | |
50 | add hl,bc ;\r | |
51 | ld a,(hl)\r | |
52 | and 0fh\r | |
53 | add a,a ;get factor\r | |
54 | ld hl,bd150_tab\r | |
55 | call add_hla\r | |
56 | ld c,(hl)\r | |
57 | inc hl\r | |
58 | ld b,(hl)\r | |
59 | ld hl,(f_cpu)\r | |
60 | ld de,(f_cpu+2)\r | |
61 | call div32_r\r | |
62 | ld bc,32*150\r | |
63 | call div32_r\r | |
64 | ld de,2\r | |
65 | or a\r | |
66 | sbc hl,de\r | |
67 | jr nc,as_ini_1\r | |
68 | ld hl,0\r | |
69 | as_ini_1:\r | |
70 | ld b,h\r | |
71 | ld c,l\r | |
72 | pop de\r | |
73 | ld hl,init_br_off\r | |
74 | add hl,de\r | |
75 | ld (hl),c\r | |
76 | inc hl\r | |
77 | ld (hl),b\r | |
78 | ex de,hl\r | |
79 | jp ioiniml\r | |
80 | \r | |
81 | \r | |
82 | bd150_tab:\r | |
83 | ; factor index baudrate orig. cp/m\r | |
84 | dw 19200/150 ; 0 19200 -\r | |
85 | dw 28800/150 ; 1 28800 50\r | |
86 | dw 38400/150 ; 2 38400 75\r | |
87 | dw 57600/150 ; 3 57600 110\r | |
88 | dw 11520/15 ; 4 115200 134.5\r | |
89 | dw 150/150 ; 5 150\r | |
90 | dw 300/150 ; 6 300\r | |
91 | dw 600/150 ; 7 600\r | |
92 | dw 1200/150 ; 8 1200\r | |
93 | dw 1800/150 ; 9 1800\r | |
94 | dw 2400/150 ;10 2400\r | |
95 | dw 3600/150 ;11 3600\r | |
96 | dw 4800/150 ;12 4800\r | |
97 | dw 7200/150 ;13 7200\r | |
98 | dw 9600/150 ;14 9600\r | |
99 | dw 19200/150 ;15 19200\r | |
100 | \r | |
101 | \r | |
102 | \r | |
103 | \r | |
104 | initab0:\r | |
105 | db 1,stat0,0 ;Disable rx/tx interrupts\r | |
106 | ;Enable baud rate generator\r | |
107 | db 1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS\r | |
108 | db 2,astc0l\r | |
109 | init_br_off equ $ - initab0\r | |
110 | dw 28\r | |
111 | db 1,cntlb0,M_MPBT ;No MP Mode, X16\r | |
112 | db 1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r | |
113 | db 0\r | |
114 | \r | |
115 | initab1:\r | |
116 | db 1,stat1,0 ;Disable rx/tx ints, disable CTS1\r | |
117 | db 1,asext1,M_BRGMOD ;Enable baud rate generator\r | |
118 | db 2,astc1l,low 3, high 3\r | |
119 | db 1,cntlb1,M_MPBT ;No MP Mode, X16\r | |
120 | db 1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r | |
121 | db 0\r | |
122 | \r | |
123 | \r | |
124 | ;--------------------------------------------------------------\r | |
125 | \r | |
126 | dseg\r | |
127 | \r | |
128 | as0ista:\r | |
129 | in0 a,(stat0)\r | |
130 | and M_RDRF\r | |
131 | ret z\r | |
132 | or 0ffh\r | |
133 | ret\r | |
134 | \r | |
135 | as1ista:\r | |
136 | in0 a,(stat1)\r | |
137 | and M_RDRF\r | |
138 | ret z\r | |
139 | or 0ffh\r | |
140 | ret\r | |
141 | \r | |
142 | \r | |
143 | as0inp:\r | |
144 | in0 a,(stat0)\r | |
145 | bit RDRF,a\r | |
146 | jr z,as0inp\r | |
147 | \r | |
148 | in0 c,(rdr0)\r | |
149 | and a,M_OVRN+M_PERR+M_FE\r | |
150 | jr z,as0in_ex\r | |
151 | \r | |
152 | in0 a,(cntla0)\r | |
153 | res EFR,a\r | |
154 | out0 (cntla0),a\r | |
155 | as0in_ex:\r | |
156 | ld a,c\r | |
157 | ret\r | |
158 | \r | |
159 | as1inp:\r | |
160 | in0 a,(stat1)\r | |
161 | bit RDRF,a\r | |
162 | jr z,as1inp\r | |
163 | \r | |
164 | in0 c,(rdr1)\r | |
165 | and a,M_OVRN+M_PERR+M_FE\r | |
166 | jr z,as1in_ex\r | |
167 | \r | |
168 | in0 a,(cntla1)\r | |
169 | res EFR,a\r | |
170 | out0 (cntla1),a\r | |
171 | as1in_ex:\r | |
172 | ld a,c\r | |
173 | ret\r | |
174 | \r | |
175 | if 0\r | |
176 | in0 a,(stat1)\r | |
177 | rlca\r | |
178 | jr nc,as1inp\r | |
179 | in0 a,rdr1\r | |
180 | ret\r | |
181 | endif\r | |
182 | \r | |
183 | \r | |
184 | as0osta:\r | |
185 | in0 a,(stat0)\r | |
186 | and M_TDRE\r | |
187 | ret z\r | |
188 | or 0ffh\r | |
189 | ret\r | |
190 | \r | |
191 | as1osta:\r | |
192 | in0 a,(stat1)\r | |
193 | and M_TDRE\r | |
194 | ret z\r | |
195 | or 0ffh\r | |
196 | ret\r | |
197 | \r | |
198 | \r | |
199 | as0out:\r | |
200 | in0 a,(stat0)\r | |
201 | and M_TDRE\r | |
202 | jr z,as0out\r | |
203 | out0 (tdr0),c\r | |
204 | ld a,c\r | |
205 | ret\r | |
206 | \r | |
207 | as1out:\r | |
208 | in0 a,(stat1)\r | |
209 | and M_TDRE\r | |
210 | jr z,as1out\r | |
211 | out0 (tdr1),c\r | |
212 | ld a,c\r | |
213 | ret\r | |
214 | \r | |
215 | end\r |