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1 | page 200\r | |
2 | \r | |
3 | ; Simple polling drivers for ASCI0 and ASCI1\r | |
4 | \r | |
5 | \r | |
6 | global as0init\r | |
7 | global as0ista,as0inp\r | |
8 | global as0osta,as0out\r | |
9 | global as1init\r | |
10 | global as1ista,as1inp\r | |
11 | global as1osta,as1out\r | |
12 | \r | |
13 | extrn as_init\r | |
14 | \r | |
15 | \r | |
16 | include config.inc\r | |
17 | include z180reg.inc\r | |
18 | \r | |
19 | dseg\r | |
20 | \r | |
21 | ;--------------------------------------------------------------\r | |
22 | ; Init Serial I/O for input and output (ASCI 0/1)\r | |
23 | ;\r | |
24 | ; b: device number\r | |
25 | ;\r | |
26 | \r | |
27 | \r | |
28 | as0init:\r | |
29 | ld c,0 ;asci channel number\r | |
30 | jp as_init\r | |
31 | \r | |
32 | as1init:\r | |
33 | ld c,1 ;asci channel number\r | |
34 | jp as_init\r | |
35 | \r | |
36 | \r | |
37 | ;--------------------------------------------------------------\r | |
38 | \r | |
39 | as0ista:\r | |
40 | in0 a,(stat0)\r | |
41 | and M_RDRF\r | |
42 | ret z\r | |
43 | or 0ffh\r | |
44 | ret\r | |
45 | \r | |
46 | as1ista:\r | |
47 | in0 a,(stat1)\r | |
48 | and M_RDRF\r | |
49 | ret z\r | |
50 | or 0ffh\r | |
51 | ret\r | |
52 | \r | |
53 | \r | |
54 | as0inp:\r | |
55 | in0 a,(stat0)\r | |
56 | bit RDRF,a\r | |
57 | jr z,as0inp\r | |
58 | \r | |
59 | in0 c,(rdr0)\r | |
60 | and a,M_OVRN+M_PERR+M_FE\r | |
61 | jr z,as0in_ex\r | |
62 | \r | |
63 | in0 a,(cntla0)\r | |
64 | res EFR,a\r | |
65 | out0 (cntla0),a\r | |
66 | as0in_ex:\r | |
67 | ld a,c\r | |
68 | ret\r | |
69 | \r | |
70 | as1inp:\r | |
71 | in0 a,(stat1)\r | |
72 | bit RDRF,a\r | |
73 | jr z,as1inp\r | |
74 | \r | |
75 | in0 c,(rdr1)\r | |
76 | and a,M_OVRN+M_PERR+M_FE\r | |
77 | jr z,as1in_ex\r | |
78 | \r | |
79 | in0 a,(cntla1)\r | |
80 | res EFR,a\r | |
81 | out0 (cntla1),a\r | |
82 | as1in_ex:\r | |
83 | ld a,c\r | |
84 | ret\r | |
85 | \r | |
86 | if 0\r | |
87 | in0 a,(stat1)\r | |
88 | rlca\r | |
89 | jr nc,as1inp\r | |
90 | in0 a,rdr1\r | |
91 | ret\r | |
92 | endif\r | |
93 | \r | |
94 | \r | |
95 | as0osta:\r | |
96 | in0 a,(stat0)\r | |
97 | and M_TDRE\r | |
98 | ret z\r | |
99 | or 0ffh\r | |
100 | ret\r | |
101 | \r | |
102 | as1osta:\r | |
103 | in0 a,(stat1)\r | |
104 | and M_TDRE\r | |
105 | ret z\r | |
106 | or 0ffh\r | |
107 | ret\r | |
108 | \r | |
109 | \r | |
110 | as0out:\r | |
111 | in0 a,(stat0)\r | |
112 | and M_TDRE\r | |
113 | jr z,as0out\r | |
114 | out0 (tdr0),c\r | |
115 | ld a,c\r | |
116 | ret\r | |
117 | \r | |
118 | as1out:\r | |
119 | in0 a,(stat1)\r | |
120 | and M_TDRE\r | |
121 | jr z,as1out\r | |
122 | out0 (tdr1),c\r | |
123 | ld a,c\r | |
124 | ret\r | |
125 | \r | |
126 | end\r |