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Commit | Line | Data |
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1 | \r | |
2 | public intinit\r | |
3 | public cpu_frq\r | |
4 | public get_tmr\r | |
5 | \r | |
6 | extrn div32_r,?pmsg\r | |
7 | extrn msg.sm,msg.recv,hwl2phy\r | |
8 | \r | |
9 | maclib z180reg.inc\r | |
10 | maclib config.inc\r | |
11 | \r | |
12 | \r | |
13 | ;----------------------------------------------------------------------\r | |
14 | \r | |
15 | dseg\r | |
16 | \r | |
17 | intinit:\r | |
18 | ld hl,ivtab ;\r | |
19 | ld a,h ;\r | |
20 | ld i,a ;\r | |
21 | out0 (il),l ;\r | |
22 | im 2\r | |
23 | \r | |
24 | ; Let all vectors point to spurious int routines.\r | |
25 | \r | |
26 | ld de,sp.int0\r | |
27 | ld bc,sp.int.len\r | |
28 | ld a,9\r | |
29 | ivt_i1:\r | |
30 | ld (hl),e\r | |
31 | inc l\r | |
32 | ld (hl),d\r | |
33 | inc l\r | |
34 | ex de,hl\r | |
35 | add hl,bc\r | |
36 | ex de,hl\r | |
37 | dec a\r | |
38 | jr nz,ivt_i1\r | |
39 | ret\r | |
40 | \r | |
41 | \r | |
42 | ;--------------------------------------------------------------------\r | |
43 | ; Spurious interrupt handler\r | |
44 | \r | |
45 | cseg ; common area\r | |
46 | sp.int0:\r | |
47 | ld a,00h\r | |
48 | jr sp.i.1\r | |
49 | sp.int.len equ $-sp.int0\r | |
50 | ld a,01h\r | |
51 | jr sp.i.1\r | |
52 | ld a,02h\r | |
53 | jr sp.i.1\r | |
54 | ld a,03h\r | |
55 | jr sp.i.1\r | |
56 | ld a,04h\r | |
57 | jr sp.i.1\r | |
58 | ld a,05h\r | |
59 | jr sp.i.1\r | |
60 | ld a,06h\r | |
61 | jr sp.i.1\r | |
62 | ld a,07h\r | |
63 | jr sp.i.1\r | |
64 | ld a,08h\r | |
65 | sp.i.1:\r | |
66 | ; out (80h),a\r | |
67 | \r | |
68 | add a,'0'\r | |
69 | ld (spi$nr),a\r | |
70 | ld hl,spi$msg\r | |
71 | call ?pmsg\r | |
72 | sp.i.2:\r | |
73 | halt\r | |
74 | jr sp.i.2\r | |
75 | \r | |
76 | spi$msg:\r | |
77 | db 13,10,'Spurious Int: '\r | |
78 | spi$nr: db '0'\r | |
79 | db 0\r | |
80 | \r | |
81 | ;--------------------------------------------------------------------\r | |
82 | ;\r | |
83 | ; Get/compute CPU clock\r | |
84 | ;\r | |
85 | ; return:\r | |
86 | ; hlde: CPU frequency (Hz)\r | |
87 | ;\r | |
88 | \r | |
89 | dseg\r | |
90 | \r | |
91 | cpu_frq:\r | |
92 | ld hl,0\r | |
93 | ld d,h\r | |
94 | ld e,l\r | |
95 | call get_tmr\r | |
96 | push de\r | |
97 | push hl\r | |
98 | \r | |
99 | ; delay ~8ms @ 18.432MHz --> 147456 clock cycles\r | |
100 | ; delay ~10ms @ 18.432MHz --> 184320 clock cycles\r | |
101 | ;\r | |
102 | \r | |
103 | ; ld hl,8192 ; 147456/18\r | |
104 | ld hl,(10240-100)*5 ; 184320/18\r | |
105 | ld de,1\r | |
106 | or a\r | |
107 | dly_lp:\r | |
108 | sbc hl,de ; 10\r | |
109 | jr nz,dly_lp ; 6/8 -> 18 cycles\r | |
110 | \r | |
111 | pop hl\r | |
112 | pop de\r | |
113 | call get_tmr\r | |
114 | \r | |
115 | ld b,h\r | |
116 | ld c,l\r | |
117 | ld de,036EEh ;18432000/(2**16) * 50\r | |
118 | ld hl,08000h ;18432000%(2**16) * 50\r | |
119 | \r | |
120 | ld a,b\r | |
121 | or a\r | |
122 | jr nz,cpuf_div\r | |
123 | ld a,c\r | |
124 | cp 2\r | |
125 | jr c,cpuf_done\r | |
126 | cpuf_div:\r | |
127 | call div32_r\r | |
128 | cpuf_done:\r | |
129 | ret\r | |
130 | \r | |
131 | ;--------------------------------------------------------------------\r | |
132 | \r | |
133 | dseg\r | |
134 | get_tmr:\r | |
135 | push de\r | |
136 | push hl\r | |
137 | ld hl,1*256 + 3 ; h = subcommand, l = command\r | |
138 | push hl\r | |
139 | ld hl,0\r | |
140 | add hl,sp\r | |
141 | ld b,6\r | |
142 | call msg.sm\r | |
143 | \r | |
144 | dec sp\r | |
145 | ld hl,0\r | |
146 | add hl,sp\r | |
147 | ld b,7 ; max receive message len\r | |
148 | call msg.recv\r | |
149 | \r | |
150 | pop bc\r | |
151 | inc sp\r | |
152 | pop hl\r | |
153 | pop de\r | |
154 | ret\r | |
155 | \r | |
156 | ;----------------------------------------------------------------------\r | |
157 | \r | |
158 | end\r |