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Commit | Line | Data |
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1 | title 'Boot loader module for CP/M 3.0'\r | |
2 | \r | |
3 | \r | |
4 | \r | |
5 | public hwinit,?init,?ldccp,?rlccp\r | |
6 | public f_cpu\r | |
7 | \r | |
8 | extrn boot,?conin\r | |
9 | extrn pr.inln,pr.crlf,pr.dec,pr.decl\r | |
10 | extrn ioini1l,msginit,mmuinit,intinit,cpu_frq\r | |
11 | extrn prt0ini,gs_rtc\r | |
12 | extrn @civec,@covec,@aivec,@aovec,@lovec\r | |
13 | extrn @cbnk,?move,?xmove\r | |
14 | \r | |
15 | maclib z180reg.inc\r | |
16 | maclib config.inc\r | |
17 | maclib version.inc\r | |
18 | \r | |
19 | \r | |
20 | ccpsize equ 0c80h\r | |
21 | \r | |
22 | ; CP/M BDOS Function Interfaces\r | |
23 | \r | |
24 | resetdsk equ 13\r | |
25 | open equ 15\r | |
26 | read equ 20\r | |
27 | setdma equ 26\r | |
28 | setmulti equ 44\r | |
29 | bdos equ 5\r | |
30 | \r | |
31 | \r | |
32 | if banked\r | |
33 | tpa$bank equ 1\r | |
34 | else\r | |
35 | tpa$bank equ 0\r | |
36 | endif\r | |
37 | \r | |
38 | \r | |
39 | dseg ; init done from banked memory\r | |
40 | \r | |
41 | hwinit:\r | |
42 | ld hl,hwini_tab\r | |
43 | call ioini1l\r | |
44 | ld a,0c3h\r | |
45 | ld hl,boot\r | |
46 | ld (0),a\r | |
47 | ld (1),hl\r | |
48 | call msginit\r | |
49 | call cpu_frq\r | |
50 | ld (f_cpu),hl\r | |
51 | ld (f_cpu+2),de\r | |
52 | call intinit ; setup interrupts and vectors\r | |
53 | ret\r | |
54 | \r | |
55 | ?init:\r | |
56 | ; ld hl,1000000000000000b ; assign console to AVRCON:\r | |
57 | ld hl,0010000000000000b ; assign console to ASCI1:\r | |
58 | ld (@civec),hl\r | |
59 | ld (@covec),hl\r | |
60 | ld hl,0000000000000000b ; assign printer to nothing:\r | |
61 | ld (@lovec),hl\r | |
62 | ld hl,0000000000000000b ; assign AUX to ASCI0:\r | |
63 | ld (@aivec),hl\r | |
64 | ld (@aovec),hl\r | |
65 | \r | |
66 | \r | |
67 | call prt0ini ; init timer\r | |
68 | ei\r | |
69 | ld c,2\r | |
70 | call gs_rtc ; get time and date\r | |
71 | \r | |
72 | xor a\r | |
73 | ld (@cbnk),a ; right now in bank 0\r | |
74 | \r | |
75 | call pr.inln ; print signon message\r | |
76 | db 13,10,13,10,'CP/M Version 3.1, Z180-Stamp BIOS v'\r | |
77 | defvers\r | |
78 | db 13,10\r | |
79 | dc 'Estimated CPU clock [Hz]: '\r | |
80 | \r | |
81 | ld hl,(f_cpu)\r | |
82 | ld de,(f_cpu+2)\r | |
83 | call pr.decl\r | |
84 | call pr.crlf\r | |
85 | ret\r | |
86 | \r | |
87 | \r | |
88 | cseg ; boot loading must be done from resident memory\r | |
89 | \r | |
90 | ; This version of the boot loader loads the CCP from a file\r | |
91 | ; called CCP.COM on the system drive (A:).\r | |
92 | \r | |
93 | ; First time, load the A:CCP.COM file into TPA\r | |
94 | ?ldccp:\r | |
95 | ld c,resetdsk\r | |
96 | call bdos\r | |
97 | xor a\r | |
98 | ld (ccp$fcb+15),a ; zero extent\r | |
99 | ld hl,0\r | |
100 | ld (fcb$nr),hl ; start at beginning of file\r | |
101 | ld de,ccp$fcb\r | |
102 | ld c,open ; open file containing CCP\r | |
103 | call bdos\r | |
104 | inc a\r | |
105 | jp z,no$ccp ; error if no file...\r | |
106 | ld de,0100h\r | |
107 | ld c,setdma ; start of TPA\r | |
108 | call bdos\r | |
109 | ld de,128\r | |
110 | ld c,setmulti ; allow up to 16k bytes\r | |
111 | call bdos\r | |
112 | ld de,ccp$fcb\r | |
113 | ld c,read ; load the thing\r | |
114 | call bdos ; read records\r | |
115 | \r | |
116 | ; now, copy CCP to bank 0 for reloading\r | |
117 | \r | |
118 | ld bc,2*256 + tpa$bank ; b: dst$bnk, c: src$bnk\r | |
119 | jr mov_ccp\r | |
120 | \r | |
121 | ; just copy in the other direction\r | |
122 | ?rlccp:\r | |
123 | ld bc,tpa$bank*256 + 2 ; b: dst$bnk, c: src$bnk\r | |
124 | mov_ccp:\r | |
125 | call ?xmove\r | |
126 | ld hl,0100h\r | |
127 | ld d,h\r | |
128 | ld e,l\r | |
129 | ld bc,ccpsize ; clone 3K, just in case\r | |
130 | call ?move\r | |
131 | ret\r | |
132 | \r | |
133 | no$ccp: ; here if we couldn't find the file\r | |
134 | call pr.inln ; report this...\r | |
135 | dc 13,10,'BIOS Err on A: No CCP.COM file'\r | |
136 | \r | |
137 | call ?conin ; get a response\r | |
138 | jr ?ldccp ; and try again\r | |
139 | \r | |
140 | \r | |
141 | ccp$fcb:db 1,'CCP ','COM',0,0,0,0\r | |
142 | ds 16\r | |
143 | fcb$nr: db 0,0,0\r | |
144 | \r | |
145 | \r | |
146 | dseg\r | |
147 | hwini_tab:\r | |
148 | db (hwini0_e-$)/2 ;count\r | |
149 | db rcr,CREFSH ;configure DRAM refresh\r | |
150 | db dcntl,CWAITIO ;wait states\r | |
151 | db ccr,M_NCD ;No Clock Divide\r | |
152 | db cmr,PHI_X2 ;X2 Clock Multiplier\r | |
153 | db omcr,~M_IOC ;Operation Mode Control Register\r | |
154 | hwini0_e:\r | |
155 | db 0 ;stop mark\r | |
156 | \r | |
157 | cseg\r | |
158 | f_cpu dw 0,0 ;detected CPU clock frequency [Hz]\r | |
159 | \r | |
160 | end\r |