cbios/misc.180

   1
   2         public intinit
   3         public bufinit
   4         public cpu_frq
   5         public get_tmr
   6
   7         public fifolst
   8
   9         extrn div32_r,?pmsg
  10         extrn msg.sm,msg.recv,hwl2phy
  11
  12         include config.inc
  13         include z180reg.inc
  14
  15
  16 ;----------------------------------------------------------------------
  17
  18         dseg
  19
  20 intinit:
  21         ld      hl,ivtab        ;
  22         ld      a,h             ;
  23         ld      i,a             ;
  24         out0    (il),l          ;
  25         im      2
  26
  27 ; Let all vectors point to spurious int routines.
  28
  29         ld      de,sp.int0
  30         ld      bc,sp.int.len
  31         ld      a,9
  32 ivt_i1:
  33         ld      (hl),e
  34         inc     l
  35         ld      (hl),d
  36         inc     l
  37         ex      de,hl
  38         add     hl,bc
  39         ex      de,hl
  40         dec     a
  41         jr      nz,ivt_i1
  42         ret
  43
  44
  45 ;--------------------------------------------------------------------
  46 ; Spurious interrupt handler
  47
  48         cseg    ; common area
  49 sp.int0:
  50         ld      a,00h
  51         jr      sp.i.1
  52 sp.int.len equ  $-sp.int0
  53         ld      a,01h
  54         jr      sp.i.1
  55         ld      a,02h
  56         jr      sp.i.1
  57         ld      a,03h
  58         jr      sp.i.1
  59         ld      a,04h
  60         jr      sp.i.1
  61         ld      a,05h
  62         jr      sp.i.1
  63         ld      a,06h
  64         jr      sp.i.1
  65         ld      a,07h
  66         jr      sp.i.1
  67         ld      a,08h
  68 sp.i.1:
  69 ;       out     (80h),a
  70
  71         add     a,'0'
  72         ld      (spi$nr),a
  73         ld      hl,spi$msg
  74         call    ?pmsg
  75 sp.i.2:
  76         halt
  77         jr      sp.i.2
  78
  79 spi$msg:
  80         db      13,10,'Spurious Int: '
  81 spi$nr: db      '0'
  82         db      0
  83
  84 ;--------------------------------------------------------------------
  85 ;
  86 ; Get/compute CPU clock
  87 ;
  88 ;    return:
  89 ;       hlde:   CPU frequency (Hz)
  90 ;
  91
  92         dseg
  93
  94 cpu_frq:
  95         ld      hl,0
  96         ld      d,h
  97         ld      e,l
  98         call    get_tmr
  99         push    de
 100         push    hl
 101
 102 ; delay  ~8ms @ 18.432MHz  --> 147456 clock cycles
 103 ; delay ~10ms @ 18.432MHz  --> 184320 clock cycles
 104 ;
 105
 106 ;       ld      hl,8192         ; 147456/18
 107         ld      hl,(10240-100)*5 ; 184320/18
 108         ld      de,1
 109         or      a
 110 dly_lp:
 111         sbc     hl,de           ; 10
 112         jr      nz,dly_lp       ; 6/8  -> 18 cycles
 113
 114         pop     hl
 115         pop     de
 116         call    get_tmr
 117
 118         ld      b,h
 119         ld      c,l
 120         ld      de,036EEh       ;18432000/(2**16) * 50
 121         ld      hl,08000h       ;18432000%(2**16) * 50
 122
 123         ld      a,b
 124         or      a
 125         jr      nz,cpuf_div
 126         ld      a,c
 127         cp      2
 128         jr      c,cpuf_done
 129 cpuf_div:
 130         call    div32_r
 131 cpuf_done:
 132         ret
 133
 134 ;--------------------------------------------------------------------
 135
 136         dseg
 137 get_tmr:
 138         push    de
 139         push    hl
 140         ld      hl,1*256 + 3            ; h = subcommand, l = command
 141         push    hl
 142         ld      hl,0
 143         add     hl,sp
 144         ld      b,6
 145         call    msg.sm
 146
 147         dec     sp
 148         ld      hl,0
 149         add     hl,sp
 150         ld      b,7                     ; max receive message len
 151         call    msg.recv
 152
 153         pop     bc
 154         inc     sp
 155         pop     hl
 156         pop     de
 157         ret
 158
 159 ;--------------------------------------------------------------------
 160
 161         dseg
 162
 163 fifolst:
 164         rept 4
 165          dw     0
 166         endm
 167
 168 ;--------------------------------------------------------------------
 169
 170         dseg
 171
 172 bufinit:
 173         ld      (ix+o.in_idx),0         ;reset pointers (empty fifo)
 174         ld      (ix+o.out_idx),0
 175         ld      a,(ix+o.id)
 176         ld      hl,fifolst
 177         ld      e,a
 178         ld      d,0
 179         add     hl,de
 180         add     hl,de
 181         push    ix
 182         pop     de
 183         cp      4
 184         jr      nc,bfi_skip
 185
 186         ld      (hl),e
 187         inc     hl
 188         ld      (hl),d
 189
 190 bfi_skip:
 191         ex      de,hl
 192         call    hwl2phy                 ;get phys. address of fifo
 193         ld      c,a
 194         ld      a,(ix+o.id)             ;fifo id
 195         or      a                       ;test if fifo 0
 196         ret     z
 197
 198         ld      b,a
 199         push    bc                      ;c: bank-addr, b: ignored
 200         push    hl                      ;address
 201         ld      c,0
 202         push    bc                      ;c: function, b:subf
 203         ld      b,5
 204         ld      h,c
 205         ld      l,c
 206         add     hl,sp
 207         call    msg.sm
 208         pop     hl
 209         pop     hl
 210         pop     hl
 211         ret
 212
 213 ;----------------------------------------------------------------------
 214
 215
 216         end