public intinit
	public cpu_frq
	public get_tmr

	extrn div32_r,?pmsg
	extrn msg.sm,msg.recv,hwl2phy

	include config.inc
	include	z180reg.inc


;----------------------------------------------------------------------

	dseg

intinit:
	ld	hl,ivtab	;
	ld	a,h		;
	ld	i,a		;
	out0	(il),l		;
	im	2

; Let all vectors point to spurious int routines.

	ld	de,sp.int0
	ld	bc,sp.int.len
	ld	a,9
ivt_i1:
	ld	(hl),e
	inc	l
	ld	(hl),d
	inc	l
	ex	de,hl
	add	hl,bc
	ex	de,hl
	dec	a
	jr	nz,ivt_i1
	ret


;--------------------------------------------------------------------
; Spurious interrupt handler

	cseg	; common area
sp.int0:
	ld	a,00h
	jr	sp.i.1
sp.int.len equ	$-sp.int0
	ld	a,01h
	jr	sp.i.1
	ld	a,02h
	jr	sp.i.1
	ld	a,03h
	jr	sp.i.1
	ld	a,04h
	jr	sp.i.1
	ld	a,05h
	jr	sp.i.1
	ld	a,06h
	jr	sp.i.1
	ld	a,07h
	jr	sp.i.1
	ld	a,08h
sp.i.1:
;	out	(80h),a

	add	a,'0'
	ld	(spi$nr),a
	ld	hl,spi$msg
	call	?pmsg
sp.i.2:
	halt
	jr	sp.i.2

spi$msg:
	db	13,10,'Spurious Int: '
spi$nr:	db	'0'
	db	0

;--------------------------------------------------------------------
;
; Get/compute CPU clock
;
;    return:
;	hlde:	CPU frequency (Hz)
;

	dseg

cpu_frq:
	ld	hl,0
	ld	d,h
	ld	e,l
	call	get_tmr
	push	de
	push	hl

; delay  ~8ms @ 18.432MHz  --> 147456 clock cycles
; delay ~10ms @ 18.432MHz  --> 184320 clock cycles
;

;	ld	hl,8192		; 147456/18
	ld	hl,(10240-100)*5 ; 184320/18
	ld	de,1
	or	a
dly_lp:
	sbc	hl,de		; 10
	jr	nz,dly_lp	; 6/8  -> 18 cycles

	pop	hl
	pop	de
	call	get_tmr

	ld	b,h
	ld	c,l
	ld	de,036EEh	;18432000/(2**16) * 50
	ld	hl,08000h	;18432000%(2**16) * 50

	ld	a,b
	or	a
	jr	nz,cpuf_div
	ld	a,c
	cp	2
	jr	c,cpuf_done
cpuf_div:
	call	div32_r
cpuf_done:
	ret

;--------------------------------------------------------------------

	dseg
get_tmr:
	push	de
	push	hl
	ld	hl,1*256 + 3		; h = subcommand, l = command
	push	hl
	ld	hl,0
	add	hl,sp
	ld	b,6
	call	msg.sm

	dec	sp
	ld	hl,0
	add	hl,sp
	ld	b,7			; max receive message len
	call	msg.recv

	pop	bc
	inc	sp
	pop	hl
	pop	de
	ret

;----------------------------------------------------------------------

	end