page	200

; Simple polling drivers for ASCI0 and ASCI1

	extrn	ioiniml

	global	as0init
	global	as0ista,as0inp
	global	as0osta,as0out
	global	as1init
	global	as1ista,as1inp
	global	as1osta,as1out


	extrn	f_cpu,add_hla,div32_r
	extrn	@ctbl

	include config.inc
	include	z180reg.inc


;--------------------------------------------------------------
; TC = (f PHI /(2*baudrate*Clock_mode)) - 2
;
; Clock_mode == 16
; 	TC = (f PHI / (32 * baudrate)) - 2
;
; br150 = baudrate/150
; 	TC = (f PHI / (32 * 150 * br150)) - 2
; 	TC = (f PHI / (32 * 150 * br150)) - 2


;
; Init Serial I/O for console input and output (ASCI1)
;

	dseg

as0init:
	ld	hl,initab0
	jr	as_init
as1init:
	ld	hl,initab1
as_init:
	push	hl

	ld	c,8			;
	mlt	bc			;
	ld	hl,@ctbl+7		;get baudrate index
	add	hl,bc			;
	ld	a,(hl)
	and	0fh
	add	a,a			;get factor
	ld	hl,bd150_tab
	call	add_hla
	ld	c,(hl)
	inc	hl
	ld	b,(hl)
	ld	hl,(f_cpu)
	ld	de,(f_cpu+2)
	call	div32_r
	ld	bc,32*150
	call	div32_r
	ld	de,2
	or	a
	sbc	hl,de
	jr	nc,as_ini_1
	ld	hl,0
as_ini_1:
	ld	b,h
	ld	c,l
	pop	de
	ld	hl,init_br_off
	add	hl,de
	ld	(hl),c
	inc	hl
	ld	(hl),b
	ex	de,hl
	jp	ioiniml


bd150_tab:
;		factor		index   baudrate	orig. cp/m
	dw	19200/150	; 0	19200		-
	dw	28800/150	; 1	28800		50
	dw	38400/150	; 2	38400		75
	dw	57600/150	; 3	57600		110
	dw	11520/15	; 4	115200		134.5
	dw	150/150		; 5	150
	dw	300/150		; 6	300
	dw	600/150		; 7	600
	dw	1200/150	; 8	1200
	dw	1800/150	; 9	1800
	dw	2400/150	;10	2400
	dw	3600/150	;11	3600
	dw	4800/150	;12	4800
	dw	7200/150	;13	7200
	dw	9600/150	;14	9600
	dw	19200/150	;15	19200




initab0:
	db	1,stat0,0		;Disable rx/tx interrupts
					;Enable baud rate generator
	db	1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS
	db	2,astc0l
init_br_off equ $ - initab0
	dw	28
	db	1,cntlb0,M_MPBT		;No MP Mode, X16
	db	1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1
	db	0

initab1:
	db	1,stat1,0		;Disable rx/tx ints, disable CTS1
	db	1,asext1,M_BRGMOD	;Enable baud rate generator
	db	2,astc1l,low 3, high 3
	db	1,cntlb1,M_MPBT		;No MP Mode, X16
	db	1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1
	db	0


;--------------------------------------------------------------

	dseg

as0ista:
	in0	a,(stat0)
	and	M_RDRF
	ret	z
	or	0ffh
	ret

as1ista:
	in0	a,(stat1)
	and	M_RDRF
	ret	z
	or	0ffh
	ret


as0inp:
	in0	a,(stat0)
	bit	RDRF,a
	jr	z,as0inp

	in0	c,(rdr0)
	and	a,M_OVRN+M_PERR+M_FE
	jr	z,as0in_ex

	in0	a,(cntla0)
	res	EFR,a
	out0	(cntla0),a
as0in_ex:
	ld	a,c
	ret

as1inp:
	in0	a,(stat1)
	bit	RDRF,a
	jr	z,as1inp

	in0	c,(rdr1)
	and	a,M_OVRN+M_PERR+M_FE
	jr	z,as1in_ex

	in0	a,(cntla1)
	res	EFR,a
	out0	(cntla1),a
as1in_ex:
	ld	a,c
	ret

    if 0
	in0	a,(stat1)
	rlca
	jr	nc,as1inp
	in0	a,rdr1
	ret
    endif


as0osta:
	in0	a,(stat0)
	and	M_TDRE
	ret	z
	or	0ffh
	ret

as1osta:
	in0	a,(stat1)
	and	M_TDRE
	ret	z
	or	0ffh
	ret


as0out:
	in0	a,(stat0)
	and	M_TDRE
	jr	z,as0out
	out0	(tdr0),c
	ld	a,c
	ret

as1out:
	in0	a,(stat1)
	and	M_TDRE
	jr	z,as1out
	out0	(tdr1),c
	ld	a,c
	ret

	end