-
- global intinit
- global bufinit
- global cpu_frq
-
- global fifolst
-
- extrn div32_r,?pmsg
- extrn msg.sm,msg.recv,hwl2phy
-
- include config.inc
- include z180reg.inc
-
-
-;----------------------------------------------------------------------
-
- dseg
-
-intinit:
- ld hl,ivtab ;
- ld a,h ;
- ld i,a ;
- out0 (il),l ;
- im 2
-
-; Let all vectors point to spurious int routines.
-
- ld de,sp.int0
- ld bc,sp.int.len
- ld a,9
-ivt_i1:
- ld (hl),e
- inc l
- ld (hl),d
- inc l
- ex de,hl
- add hl,bc
- ex de,hl
- dec a
- jr nz,ivt_i1
- ret
-
-
-;--------------------------------------------------------------------
-; Spurious interrupt handler
-
- cseg ; common area
-sp.int0:
- ld a,00h
- jr sp.i.1
-sp.int.len equ $-sp.int0
- ld a,01h
- jr sp.i.1
- ld a,02h
- jr sp.i.1
- ld a,03h
- jr sp.i.1
- ld a,04h
- jr sp.i.1
- ld a,05h
- jr sp.i.1
- ld a,06h
- jr sp.i.1
- ld a,07h
- jr sp.i.1
- ld a,08h
-sp.i.1:
-; out (80h),a
-
- add a,'0'
- ld (spi$nr),a
- ld hl,spi$msg
- call ?pmsg
-sp.i.2:
- halt
- jr sp.i.2
-
-spi$msg:
- db 13,10,'Spurious Int: '
-spi$nr: db '0'
- db 0
-
-;--------------------------------------------------------------------
-;
-; Get/compute CPU clock
-;
-; return:
-; hlde: CPU frequency (Hz)
-;
-
- dseg
-
-cpu_frq:
- ld hl,0
- ld d,h
- ld e,l
- call get_timer
- push de
- push hl
-
-; delay ~8ms @ 18.432MHz --> 147456 clock cycles
-; delay ~10ms @ 18.432MHz --> 184320 clock cycles
-;
-
-; ld hl,8192 ; 147456/18
- ld hl,(10240-100)*5 ; 184320/18
- ld de,1
- or a
-dly_lp:
- sbc hl,de ; 10
- jr nz,dly_lp ; 6/8 -> 18 cycles
-
- pop hl
- pop de
- call get_timer
-
- ld b,h
- ld c,l
- ld de,036EEh ;18432000/(2**16) * 50
- ld hl,08000h ;18432000%(2**16) * 50
-
- ld a,b
- or a
- jr nz,cpuf_div
- ld a,c
- cp 2
- jr c,cpuf_done
-cpuf_div:
- call div32_r
-cpuf_done:
- ret
-
-;--------------------------------------------------------------------
-
-get_timer:
- push de
- push hl
- ld hl,1*256 + 3 ; d = subcommand, e = command
- push hl
- ld hl,0
- add hl,sp
- ld b,6
- call msg.sm
-
- dec sp
- ld hl,0
- add hl,sp
- ld b,7 ; max receive message len
- call msg.recv
-
- pop bc
- inc sp
- pop hl
- pop de
- ret
-
-;--------------------------------------------------------------------
-
- cseg
-
-fifolst:
- rept 4
- dw 0
- db 0
- endm
-
-;--------------------------------------------------------------------
-
- dseg
-
-bufinit:
- ld a,(ix+o.id)
- cp 4
- jr nc,bfi_doit2
-
- ld hl,fifolst
- ld e,a
- ld d,0
- add hl,de
- add hl,de
- add hl,de
-
- if 0
- ld e,(hl)
- inc hl
- ld d,(hl)
- dec hl
- ld a,e
- or d
- jr z,bfi_doit
-
-; TODO: address translation
- push de
- pop ix
- ret
- endif
-
-bfi_doit:
- push ix
- pop de
-; TODO: address translation
- ld (hl),e
- inc hl
- ld (hl),d
- ld a,(ix+o.id)
- or a
- jr nz,bfi_doit2
-
- ld hl,fifolst
- ld (040h),hl
- ld (040h+2),a
-
-bfi_doit2:
- ld (ix+o.in_idx),0 ;reset pointers
- ld (ix+o.out_idx),0
-
- push ix ;get phys. address of fifo
- pop hl
- call hwl2phy
- ex de,hl
- ld c,a
- ld a,(ix+o.id) ;fifo id
- or a ;test if fifo 0
- jr nz,bfi_1
-
- out (AVRINT5),a
- ret
-
-bfi_1:
- ld hl,bfi_msg_end
- ld (hl),c
- dec hl
- ld (hl),d
- dec hl
- ld (hl),e
- dec hl
- ld (hl),a
- dec hl
- ld b,bfi_msg_len
- call msg.sm
- ret
-
-bfi_msg:
- db 0 ;function: 0
- db 0 ;subfunc: gets overwritten with buf id
- dw 0 ;physical
- db 0 ; address
-bfi_msg_len equ $ - bfi_msg
-bfi_msg_end equ $ - 1
-
-;----------------------------------------------------------------------
-
-
- end
+\r
+ public intinit\r
+ public cpu_frq\r
+ public get_tmr\r
+\r
+ extrn div32_r,?pmsg\r
+ extrn msg.sm,msg.recv,hwl2phy\r
+\r
+ include config.inc\r
+ include z180reg.inc\r
+\r
+\r
+;----------------------------------------------------------------------\r
+\r
+ dseg\r
+\r
+intinit:\r
+ ld hl,ivtab ;\r
+ ld a,h ;\r
+ ld i,a ;\r
+ out0 (il),l ;\r
+ im 2\r
+\r
+; Let all vectors point to spurious int routines.\r
+\r
+ ld de,sp.int0\r
+ ld bc,sp.int.len\r
+ ld a,9\r
+ivt_i1:\r
+ ld (hl),e\r
+ inc l\r
+ ld (hl),d\r
+ inc l\r
+ ex de,hl\r
+ add hl,bc\r
+ ex de,hl\r
+ dec a\r
+ jr nz,ivt_i1\r
+ ret\r
+\r
+\r
+;--------------------------------------------------------------------\r
+; Spurious interrupt handler\r
+\r
+ cseg ; common area\r
+sp.int0:\r
+ ld a,00h\r
+ jr sp.i.1\r
+sp.int.len equ $-sp.int0\r
+ ld a,01h\r
+ jr sp.i.1\r
+ ld a,02h\r
+ jr sp.i.1\r
+ ld a,03h\r
+ jr sp.i.1\r
+ ld a,04h\r
+ jr sp.i.1\r
+ ld a,05h\r
+ jr sp.i.1\r
+ ld a,06h\r
+ jr sp.i.1\r
+ ld a,07h\r
+ jr sp.i.1\r
+ ld a,08h\r
+sp.i.1:\r
+; out (80h),a\r
+\r
+ add a,'0'\r
+ ld (spi$nr),a\r
+ ld hl,spi$msg\r
+ call ?pmsg\r
+sp.i.2:\r
+ halt\r
+ jr sp.i.2\r
+\r
+spi$msg:\r
+ db 13,10,'Spurious Int: '\r
+spi$nr: db '0'\r
+ db 0\r
+\r
+;--------------------------------------------------------------------\r
+;\r
+; Get/compute CPU clock\r
+;\r
+; return:\r
+; hlde: CPU frequency (Hz)\r
+;\r
+\r
+ dseg\r
+\r
+cpu_frq:\r
+ ld hl,0\r
+ ld d,h\r
+ ld e,l\r
+ call get_tmr\r
+ push de\r
+ push hl\r
+\r
+; delay ~8ms @ 18.432MHz --> 147456 clock cycles\r
+; delay ~10ms @ 18.432MHz --> 184320 clock cycles\r
+;\r
+\r
+; ld hl,8192 ; 147456/18\r
+ ld hl,(10240-100)*5 ; 184320/18\r
+ ld de,1\r
+ or a\r
+dly_lp:\r
+ sbc hl,de ; 10\r
+ jr nz,dly_lp ; 6/8 -> 18 cycles\r
+\r
+ pop hl\r
+ pop de\r
+ call get_tmr\r
+\r
+ ld b,h\r
+ ld c,l\r
+ ld de,036EEh ;18432000/(2**16) * 50\r
+ ld hl,08000h ;18432000%(2**16) * 50\r
+\r
+ ld a,b\r
+ or a\r
+ jr nz,cpuf_div\r
+ ld a,c\r
+ cp 2\r
+ jr c,cpuf_done\r
+cpuf_div:\r
+ call div32_r\r
+cpuf_done:\r
+ ret\r
+\r
+;--------------------------------------------------------------------\r
+\r
+ dseg\r
+get_tmr:\r
+ push de\r
+ push hl\r
+ ld hl,1*256 + 3 ; h = subcommand, l = command\r
+ push hl\r
+ ld hl,0\r
+ add hl,sp\r
+ ld b,6\r
+ call msg.sm\r
+\r
+ dec sp\r
+ ld hl,0\r
+ add hl,sp\r
+ ld b,7 ; max receive message len\r
+ call msg.recv\r
+\r
+ pop bc\r
+ inc sp\r
+ pop hl\r
+ pop de\r
+ ret\r
+\r
+;----------------------------------------------------------------------\r
+\r
+ end\r
projects / z180-stamp-cpm3.git / blobdiff