db 0 ;absolute device #\r
db 0 ;relative device\r
db 0 ;iflags\r
- db 0 ;fflags\r
+ db M_CREAD+M_CRTS_IFLOW+M_CCTS_OFLOW ;fflags\r
db M_CS8 ;cflags\r
o.absdev equ 0\r
o.reldev equ 1\r
db 0 ;absolute device #\r
db 1 ;relative device\r
db 0 ;iflags\r
- db 0 ;fflags\r
+ db M_CREAD ;fflags\r
db M_CS8 ;cflags\r
\r
db 0\r
;\r
\r
asci_ioctl:\r
+ ld a,b\r
+ cp 1\r
+ jr nz,asioc_1\r
+ ld a,(INIDONE)\r
+ and 80h\r
+ cp INIDONEVAL\r
+ ret z\r
+asioc_1:\r
push hl\r
ex (sp),ix\r
ld (ix+o.absdev),b\r
ld a,(hl) ;get baudrate index\r
call as_br_div\r
ld c,astc0l\r
- ld a,l\r
- call out_asci_reg\r
- inc c\r
- ld a,h\r
- call out_asci_reg\r
-\r
+ call out_asci_reg_hl\r
\r
ld c,cntlb0\r
ld a,M_MPBT ;No MP Mode, X16\r
; Get the current serial port settings.\r
\r
func_tcgeta:\r
- ld a,d\r
- or e\r
- ld a,0ffh\r
- jr z,fgeta_e\r
+ call chk_ptr\r
\r
ld a,(ix+o.iflags)\r
call b_st_a\r
dec de\r
dec de\r
xor a\r
-fgeta_e:\r
ret\r
\r
-\r
;--------------------------------------------------------------\r
; Set the current serial port settings.\r
\r
func_tcseta:\r
- ld a,d\r
- or e\r
- ld a,0ffh\r
- jr z,fseta_e\r
+ call chk_ptr\r
\r
call asci_stop\r
\r
call init_st\r
pop de\r
xor a\r
-fseta_e:\r
ret\r
\r
-\r
;--------------------------------------------------------------\r
; Allow the output buffer to drain\r
\r
\r
;--------------------------------------------------------------\r
\r
+chk_ptr:\r
+ ld a,e\r
+ or d\r
+ ret nz\r
+ cpl\r
+ pop hl\r
+ ret\r
+\r
+;--------------------------------------------------------------\r
+\r
asci_stop:\r
ld c,stat0 ;Disable rx/tx interrupts\r
xor a ;\r
\r
out_asci_reg:\r
push bc\r
- ld b,a\r
- ld a,c\r
- cp astc0l ;astc0/1 are 16 bit\r
- jr c,$+5\r
- add a,(ix+o.reldev)\r
- add a,(ix+o.reldev)\r
- ld c,a\r
- ld a,b\r
+ bit 0,(ix+o.reldev)\r
+ jr z,$+3\r
+ inc c\r
ld b,0\r
out (c),a\r
pop bc\r
ret\r
\r
+;--------------------------------------------------------------\r
+; output 16 bit value to asci0/1 register\r
+;\r
+; c: register address\r
+; hl: value\r
+; a destroyed\r
+\r
+out_asci_reg_hl:\r
+ ld a,b ;save b\r
+ bit 0,(ix+o.reldev)\r
+ jr z,$+4\r
+ inc c\r
+ inc c\r
+ ld b,0\r
+ out (c),l\r
+ inc c\r
+ out (c),h\r
+ ld b,a\r
+ ret\r
+\r
;--------------------------------------------------------------\r
; baud rate divider\r
;\r
ld a,b\r
cp s0.rx_len/4\r
jr nc,a0i_1\r
+ bit CRTS_IFLOW,(ix+oint.fflags)\r
+ jr z,a0i_1\r
di\r
in0 a,(cntla0)\r
and ~M_RTS0 ;assert RTS\r
cseg\r
rtxisvjmp0:\r
call isv_sw\r
- dw rxtxi0\r
+ dw asci0_int\r
+\r
rtxisvjmp1:\r
call isv_sw\r
- dw rxtxi1\r
+ dw asci1_int\r
\r
;--------------------------------------------------------------\r
-; ASCI 0 Transmit/Receive interupt routines\r
+; ASCI 0/1 Transmit/Receive interupt routines\r
+\r
+ .lall\r
+asci_int macro dev\r
+ local rxi_2,rxi_4\r
\r
- dseg\r
-rxtxi0:\r
push ix\r
-rxtxi0_lp0:\r
- ld ix,s0.inbuf ;\r
-rxtxi0_lp1:\r
- in0 a,(stat0) ;receive flag set?\r
- jp p,rxtxi0_1 ;RDRF == Bit 7\r
+rxtxi&dev&_lp0:\r
+ ld ix,s&dev&.inbuf ;\r
+rxtxi&dev&_lp1:\r
+ in0 a,(stat&dev) ;receive flag set?\r
+ jp p,txi&dev ;RDRF == Bit 7\r
and M_OVRN+M_PERR+M_FE\r
ld e,a\r
\r
- in0 a,(asext0)\r
+ in0 a,(asext&dev)\r
and M_BREAK\r
or e\r
ld e,a\r
\r
- in0 d,(cntla0) ;\r
+ in0 d,(cntla&dev) ;\r
res EFR,d ;\r
- out0 (cntla0),d\r
-\r
+ out0 (cntla&dev),d\r
\r
ld c,(ix+o.in_idx) ;\r
ld b,0\r
- ld hl,s0.inbuf ;\r
+ ld hl,s&dev&.inbuf ;\r
add hl,bc\r
\r
- in0 a,(rdr0) ;\r
+ in0 a,(rdr&dev) ;\r
ld (hl),a\r
;todo: break detection\r
;todo: parity, framing overrun error\r
\r
-\r
ld e,(ix+oint.fflags)\r
bit IXON,e\r
- jr z,rxtxi0_2\r
-\r
+ jr z,rxi_2\r
;todo: test XON/XOFF\r
\r
-rxtxi0_2:\r
-\r
+rxi_2:\r
\r
ld a,c ;increment buffer in pointer\r
inc a ;\r
ld c,a\r
\r
sub (ix+o.out_idx) ;\r
- jr z,rxtxi0_lp1 ;skip if buffer is full\r
+ jr z,rxtxi&dev&_lp1 ;skip if buffer is full\r
\r
ld (ix+o.in_idx),c ;\r
\r
jr nc,$+3 ;\r
adc b ;\r
\r
- cp s0.tx_len*3/4\r
- jr c,rxi0_noflow\r
+ cp s&dev&.tx_len*3/4\r
+ jr c,rxi&dev&_noflow\r
\r
+ if dev=0\r
bit CRTS_IFLOW,e\r
- jr z,rxtxi0_4\r
+ jr z,rxi_4\r
\r
set EFR,d\r
set RTS0,d ;RTS inactive\r
- out0 (cntla0),d ;\r
+ out0 (cntla&dev),d ;\r
+ endif\r
\r
-rxtxi0_4:\r
+rxi_4:\r
bit IXOFF,e\r
- jr z,rxtxi0_lp1\r
+ jr z,rxtxi&dev&_lp1\r
;todo: send XOFF\r
\r
-rxi0_noflow:\r
- jr rxtxi0_lp1\r
+rxi&dev&_noflow:\r
+ jr rxtxi&dev&_lp1\r
\r
\r
-rxtxi0_1:\r
+txi&dev:\r
ld e,a\r
bit TDRE,e ;TX int?\r
- jr z,rxtxi0_e ;\r
-\r
-\r
- ld ix,s0.outbuf ;\r
-\r
- ld a,(ix+o.out_idx) ;\r
- cp (ix+o.in_idx) ;if index.in == index.out\r
- jr z,?0ti_2 ; buffer empty\r
-\r
- ld hl,s0.outbuf ;\r
- ld c,a\r
- ld b,0\r
- add hl,bc\r
- ld b,(hl)\r
- out0 (tdr0),b ; 7\r
+ jr z,rxtxi&dev&_exit\r
+\r
+ ;todo: xon/xoff\r
+\r
+ ld hl,s&dev&.outbuf+o.in_idx ;[in]\r
+ ld a,(hl) ;\r
+ inc hl ;[out]\r
+ ld c,(hl) ;\r
+ cp c ;\r
+ jr z,txi&dev&_empty ;\r
+ inc hl ;fifo base\r
+ ld b,0 ;\r
+ add hl,bc ;\r
+ ld a,(hl) ;\r
+ out0 (tdr&dev),a ;\r
+ inc c ;\r
+ ld a,(s&dev&.outbuf+o.mask) ;\r
+ and c ;\r
+ ld (s&dev&.outbuf+o.out_idx),a ;\r
\r
- inc a\r
- and (ix+o.mask)\r
- ld (ix+o.out_idx),a\r
- jr rxtxi0_lp0\r
+ jr rxtxi&dev&_lp0\r
\r
-?0ti_2:\r
+txi&dev&_empty:\r
res TIE,e ;disable tx-int\r
- out0 (stat0),e ; 5\r
+ out0 (stat&dev),e ; 5\r
\r
-rxtxi0_e:\r
+rxtxi&dev&_exit:\r
pop ix\r
ret\r
-\r
-\r
-;--------------------------------------------------------------\r
-; ASCI 1 Transmit/Receive interupt routines\r
+ endm\r
\r
dseg\r
-rxtxi1:\r
- in0 e,(stat1) ;receive flag set? 5\r
- jp p,txi1_0 ;\r
-\r
- in0 d,(rdr1) ;todo: break detection 9\r
- bit FE,e ;framing error?\r
- jr nz,??ri_1\r
-\r
- push ix\r
- ld ix,s1.inbuf ;\r
- ld hl,s1.inbuf ;\r
- ld c,(ix+o.in_idx) ;\r
- ld b,0\r
- add hl,bc\r
- ld (hl),d\r
-\r
- ld a,c ;\r
- inc a\r
- and (ix+o.mask)\r
- cp (ix+o.out_idx) ;\r
- jr z,$+5 ;skip if buffer is full\r
- ld (ix+o.in_idx),a\r
- pop ix\r
-??ri_1:\r
- in0 a,(cntla1) ; 1\r
- res EFR,a ;\r
- out0 (cntla1),a ; 1\r
- ret\r
-\r
-txi1_0:\r
- push ix\r
- ld ix,s1.outbuf ;\r
-\r
- ld a,(ix+o.out_idx) ;\r
- cp (ix+o.in_idx) ;if index.in == index.out\r
- jr z,??ti_2 ; buffer empty\r
+;--------------------------------------------------------------\r
+; ASCI 0 Transmit/Receive interupt routines\r
\r
- ld hl,s1.outbuf ;\r
- ld c,a\r
- ld b,0\r
- add hl,bc\r
- ld l,(hl)\r
- out0 (tdr1),l ; 7\r
-\r
- inc a\r
- and (ix+o.mask)\r
- ld (ix+o.out_idx),a\r
- jr ??ti_3\r
-??ti_2:\r
- res TIE,e ;disable tx-int\r
- out0 (stat1),e ; 5\r
-??ti_3:\r
- pop ix\r
- ret\r
+asci0_int:\r
+ asci_int 0\r
\r
+;--------------------------------------------------------------\r
+; ASCI 1 Transmit/Receive interupt routines\r
\r
+asci1_int:\r
+ asci_int 1\r
\r
end\r
projects / z180-stamp-cpm3.git / blobdiff