- global add_hla,div32_16
+ global add_hla,div32_16,div32_r
global ioiniml,ioini1l
global intinit
global bufinit
include config.inc
include z180reg.inc
-;--------------------------------------------------------------
-;
+
+;--------------------------------------------------------------------
; add a to hl
;
; return:
inc h
ret
+;--------------------------------------------------------------------
+; rounded div 32 by 16 bit
+;
+; HLDE: Dividend (x)
+; BC: Divisor (y)
+; return:
+; HLDE: Rounded Quotient (q)
+; BC: Remainder (r)
+
+ cseg
+
+div32_r:
+ push bc
+ srl b ;y/2
+ rr c
+ add hl,bc ;low x + y/2
+ pop bc
+ jr nc,div_r1
+ inc hl
+div_r1:
+ ;fall thru
+
;--------------------------------------------------------------------
; Divide 32 bit by 16
;
-; HLDE: Divident (x)
+; DEHL: Dividend (x)
; BC: Divisor (y)
;
; return:
-; HLDE: Quotient
+; DEHL: Quotient
; BC: Reminder
cseg ; common area
push de ;save alternate registers (de,bc)
push bc
exx ;high
- push de ;low x
- push bc ;low y
- ld bc,0 ;bc = high y = 0
- ld d,b ;de = high r = 0
- ld e,c
- ex de,hl ;de = x, hl = r
+ push hl ;lx
+ push bc ;ly
+ ld bc,0 ;bc = hy = 0
+ ld h,b ;hl = hr = 0
+ ld l,c
+ ;de = x, hl = r
exx ;low
- pop bc ;bc' = low y
- ex (sp),hl ;hl' = low x, save alternate hl
- ld de,0 ;de' = low r = 0
+ pop bc ;bc' = ly
+ ex (sp),hl ;hl' = lx, save alternate hl
+ ld de,0 ;de' = lr = 0
ex de,hl ;de = x, hl = r
exx ;high
ld a,32 ;count
;
-; divide x/y
-; x: hl
-; y: de
-; result:
-; x/y: hl
-; rem: de
+; start:
+; de: x (de: hx, de': lx)
+; bc: y (bc: hy, bc': ly)
+; hl: 0
+;
div_lp: ;do
exx ; low
ex de,hl ; x
dec a ;
jr nz,div_lp ;while (--count)
- ex de,hl ; q
+; result:
+; de: q (de: hq, de': lq)
+; hl: r (hl: hr, hl': lr)
+
exx ;low
- ex de,hl ; q
+ ex de,hl ;hl = lq, de = lr
- ex (sp),hl ;low q
- push de ;low r
+ ex (sp),hl ;lq
+ push de ;lr
exx ;high
- pop bc ;bc = r
- pop de ;de = low q
+ pop bc ;bc = lr
+ pop hl ;de = lq
exx ;low
pop bc ;restore alternate registers
ld d,h
ld e,l
call get_timer
- push hl
push de
+ push hl
; delay ~8ms @ 18.432MHz --> 147456 clock cycles
; delay ~10ms @ 18.432MHz --> 184320 clock cycles
sbc hl,de ; 10
jr nz,dly_lp ; 6/8 -> 18
- pop de
pop hl
+ pop de
call get_timer
-; ld hl,4 ; round
- ld hl,5 ; round
- add hl,de
- ex de,hl
- ld hl,0
ld bc,10
- call div32_16
- ld b,d
- ld c,e
- ld hl,00119h ;18432000/(2**16)
- ld de,04000h ;18432000%(2**16)
+ call div32_r
+ ld b,h
+ ld c,l
+ ld de,00119h ;18432000/(2**16)
+ ld hl,04000h ;18432000%(2**16)
ld a,b
or a
cp 2
jr c,cpuf_done
cpuf_div:
- call div32_16
+ call div32_r
cpuf_done:
ret
;--------------------------------------------------------------------
get_timer:
- push hl
push de
+ push hl
ld hl,1*256 + 3 ; d = subcommand, e = command
push hl
ld hl,0
pop bc
inc sp
- pop de
pop hl
+ pop de
ret
;--------------------------------------------------------------------