X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp-cpm3.git/blobdiff_plain/c5868b68107012ee3bd827de8229ecc1037b5b69..7f282135daa6c08cfeb789b65569e7f1dc728570:/cbios/misc.180

diff --git a/cbios/misc.180 b/cbios/misc.180
index 439fb75..10eb83c 100644
--- a/cbios/misc.180
+++ b/cbios/misc.180
@@ -1,216 +1,158 @@
-
-	public intinit
-	public bufinit
-	public cpu_frq
-	public get_tmr
-
-	public fifolst
-
-	extrn div32_r,?pmsg
-	extrn msg.sm,msg.recv,hwl2phy
-
-	include config.inc
-	include	z180reg.inc
-
-
-;----------------------------------------------------------------------
-
-	dseg
-
-intinit:
-	ld	hl,ivtab	;
-	ld	a,h		;
-	ld	i,a		;
-	out0	(il),l		;
-	im	2
-
-; Let all vectors point to spurious int routines.
-
-	ld	de,sp.int0
-	ld	bc,sp.int.len
-	ld	a,9
-ivt_i1:
-	ld	(hl),e
-	inc	l
-	ld	(hl),d
-	inc	l
-	ex	de,hl
-	add	hl,bc
-	ex	de,hl
-	dec	a
-	jr	nz,ivt_i1
-	ret
-
-
-;--------------------------------------------------------------------
-; Spurious interrupt handler
-
-	cseg	; common area
-sp.int0:
-	ld	a,00h
-	jr	sp.i.1
-sp.int.len equ	$-sp.int0
-	ld	a,01h
-	jr	sp.i.1
-	ld	a,02h
-	jr	sp.i.1
-	ld	a,03h
-	jr	sp.i.1
-	ld	a,04h
-	jr	sp.i.1
-	ld	a,05h
-	jr	sp.i.1
-	ld	a,06h
-	jr	sp.i.1
-	ld	a,07h
-	jr	sp.i.1
-	ld	a,08h
-sp.i.1:
-;	out	(80h),a
-
-	add	a,'0'
-	ld	(spi$nr),a
-	ld	hl,spi$msg
-	call	?pmsg
-sp.i.2:
-	halt
-	jr	sp.i.2
-
-spi$msg:
-	db	13,10,'Spurious Int: '
-spi$nr:	db	'0'
-	db	0
-
-;--------------------------------------------------------------------
-;
-; Get/compute CPU clock
-;
-;    return:
-;	hlde:	CPU frequency (Hz)
-;
-
-	dseg
-
-cpu_frq:
-	ld	hl,0
-	ld	d,h
-	ld	e,l
-	call	get_tmr
-	push	de
-	push	hl
-
-; delay  ~8ms @ 18.432MHz  --> 147456 clock cycles
-; delay ~10ms @ 18.432MHz  --> 184320 clock cycles
-;
-
-;	ld	hl,8192		; 147456/18
-	ld	hl,(10240-100)*5 ; 184320/18
-	ld	de,1
-	or	a
-dly_lp:
-	sbc	hl,de		; 10
-	jr	nz,dly_lp	; 6/8  -> 18 cycles
-
-	pop	hl
-	pop	de
-	call	get_tmr
-
-	ld	b,h
-	ld	c,l
-	ld	de,036EEh	;18432000/(2**16) * 50
-	ld	hl,08000h	;18432000%(2**16) * 50
-
-	ld	a,b
-	or	a
-	jr	nz,cpuf_div
-	ld	a,c
-	cp	2
-	jr	c,cpuf_done
-cpuf_div:
-	call	div32_r
-cpuf_done:
-	ret
-
-;--------------------------------------------------------------------
-
-	dseg
-get_tmr:
-	push	de
-	push	hl
-	ld	hl,1*256 + 3		; h = subcommand, l = command
-	push	hl
-	ld	hl,0
-	add	hl,sp
-	ld	b,6
-	call	msg.sm
-
-	dec	sp
-	ld	hl,0
-	add	hl,sp
-	ld	b,7			; max receive message len
-	call	msg.recv
-
-	pop	bc
-	inc	sp
-	pop	hl
-	pop	de
-	ret
-
-;--------------------------------------------------------------------
-
-	cseg
-
-fifolst:
-	rept 4
-	 dw	0
-	endm
-
-;--------------------------------------------------------------------
-
-	dseg
-
-bufinit:
-	ld	(ix+o.in_idx),0		;reset pointers (empty fifo)
-	ld	(ix+o.out_idx),0
-	ld	a,(ix+o.id)
-	ld	hl,fifolst
-	ld	e,a
-	ld	d,0
-	add	hl,de
-	add	hl,de
-	push	ix
-	pop	de
-	cp	4
-	jr	nc,bfi_skip
-
-	ld	(hl),e
-	inc	hl
-	ld	(hl),d
-
-bfi_skip:
-	ex	de,hl
-	call	hwl2phy			;get phys. address of fifo
-	ld	c,a
-	ld	a,(ix+o.id)		;fifo id
-	or	a			;test if fifo 0
-	ret	z
-
-	ld	b,a
-	push	bc			;c: bank-addr, b: ignored
-	push	hl			;address
-	ld	c,0
-	push	bc			;c: function, b:subf
-	ld	b,5
-	ld	h,c
-	ld	l,c
-	add	hl,sp
-	call	msg.sm
-	pop	hl
-	pop	hl
-	pop	hl
-	ret
-
-;----------------------------------------------------------------------
-
-
-	end
+
+	public intinit
+	public cpu_frq
+	public get_tmr
+
+	extrn div32_r,?pmsg
+	extrn msg.sm,msg.recv,hwl2phy
+
+	include config.inc
+	include	z180reg.inc
+
+
+;----------------------------------------------------------------------
+
+	dseg
+
+intinit:
+	ld	hl,ivtab	;
+	ld	a,h		;
+	ld	i,a		;
+	out0	(il),l		;
+	im	2
+
+; Let all vectors point to spurious int routines.
+
+	ld	de,sp.int0
+	ld	bc,sp.int.len
+	ld	a,9
+ivt_i1:
+	ld	(hl),e
+	inc	l
+	ld	(hl),d
+	inc	l
+	ex	de,hl
+	add	hl,bc
+	ex	de,hl
+	dec	a
+	jr	nz,ivt_i1
+	ret
+
+
+;--------------------------------------------------------------------
+; Spurious interrupt handler
+
+	cseg	; common area
+sp.int0:
+	ld	a,00h
+	jr	sp.i.1
+sp.int.len equ	$-sp.int0
+	ld	a,01h
+	jr	sp.i.1
+	ld	a,02h
+	jr	sp.i.1
+	ld	a,03h
+	jr	sp.i.1
+	ld	a,04h
+	jr	sp.i.1
+	ld	a,05h
+	jr	sp.i.1
+	ld	a,06h
+	jr	sp.i.1
+	ld	a,07h
+	jr	sp.i.1
+	ld	a,08h
+sp.i.1:
+;	out	(80h),a
+
+	add	a,'0'
+	ld	(spi$nr),a
+	ld	hl,spi$msg
+	call	?pmsg
+sp.i.2:
+	halt
+	jr	sp.i.2
+
+spi$msg:
+	db	13,10,'Spurious Int: '
+spi$nr:	db	'0'
+	db	0
+
+;--------------------------------------------------------------------
+;
+; Get/compute CPU clock
+;
+;    return:
+;	hlde:	CPU frequency (Hz)
+;
+
+	dseg
+
+cpu_frq:
+	ld	hl,0
+	ld	d,h
+	ld	e,l
+	call	get_tmr
+	push	de
+	push	hl
+
+; delay  ~8ms @ 18.432MHz  --> 147456 clock cycles
+; delay ~10ms @ 18.432MHz  --> 184320 clock cycles
+;
+
+;	ld	hl,8192		; 147456/18
+	ld	hl,(10240-100)*5 ; 184320/18
+	ld	de,1
+	or	a
+dly_lp:
+	sbc	hl,de		; 10
+	jr	nz,dly_lp	; 6/8  -> 18 cycles
+
+	pop	hl
+	pop	de
+	call	get_tmr
+
+	ld	b,h
+	ld	c,l
+	ld	de,036EEh	;18432000/(2**16) * 50
+	ld	hl,08000h	;18432000%(2**16) * 50
+
+	ld	a,b
+	or	a
+	jr	nz,cpuf_div
+	ld	a,c
+	cp	2
+	jr	c,cpuf_done
+cpuf_div:
+	call	div32_r
+cpuf_done:
+	ret
+
+;--------------------------------------------------------------------
+
+	dseg
+get_tmr:
+	push	de
+	push	hl
+	ld	hl,1*256 + 3		; h = subcommand, l = command
+	push	hl
+	ld	hl,0
+	add	hl,sp
+	ld	b,6
+	call	msg.sm
+
+	dec	sp
+	ld	hl,0
+	add	hl,sp
+	ld	b,7			; max receive message len
+	call	msg.recv
+
+	pop	bc
+	inc	sp
+	pop	hl
+	pop	de
+	ret
+
+;----------------------------------------------------------------------
+
+	end