From: Leo C <erbl259-lmu@yahoo.de>
Date: Mon, 12 Oct 2015 09:22:47 +0000 (+0200)
Subject: Makefile: add dist target
X-Git-Tag: hexrel-6.7~12
X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp-cpm3.git/commitdiff_plain/fcf62661f0fb0e1db1dc61b39983f36e6e50bfcf

Makefile: add dist target
---

diff --git a/cbios/.gitignore b/cbios/.gitignore
index 659ccd6..679ec97 100644
--- a/cbios/.gitignore
+++ b/cbios/.gitignore
@@ -5,7 +5,10 @@
 *.map
 *.rel
 *.hex
-*.spr
+bnkbdos3.spr
+bnkbios3.spr
+resbdos3.spr
+modebaud.inc
 cpm3_*.sys
 *.zip
 autorevision.cache
diff --git a/cbios/Makefile b/cbios/Makefile
index f8018d0..39a747a 100644
--- a/cbios/Makefile
+++ b/cbios/Makefile
@@ -11,25 +11,32 @@ INC := config.inc z180reg.inc z180.lib
 OBJ := $(SRC:.180=.rel)
 
 
-$(foreach X,$(subst =,:=,$(filter VCS_%,\
-	$(shell autorevision -t sh -o $(CURDIR)/autorevision.cache))),$(eval $X))
+$(foreach X,$(subst =,:=,$(subst ",,$(filter VCS_%,\
+	$(shell autorevision -t sh -o $(CURDIR)/autorevision.cache)))),$(eval $X))
 
 VERS := $(shell echo "$(VCS_TAG)" | sed -e 's/hexrel-/0./g' -e 's/^v//g')
 
-ifneq ($(VCS_TICK),"0")
-  VERS := $(VERS).$(subst ",,$(VCS_TICK))
+ifneq ($(VCS_TICK),0)
+  VERS := $(VERS).$(VCS_TICK)
 endif
-ifneq ($(VCS_BRANCH),"master")
-  VERS := $(VERS)-$(subst ",,$(VCS_BRANCH))
+ifneq ($(VCS_BRANCH),master)
+  VERS := $(VERS)-$(VCS_BRANCH)
 endif
-ifeq ($(VCS_WC_MODIFIED),"1")
+ifeq ($(VCS_WC_MODIFIED),1)
   VERS := $(VERS)-dirty
 endif
 
 
 SYSFILE = cpm3_$(VERS).sys
 MAPFILE = bnkbios3_$(VERS).map
-ZIPFILE = cpm3_$(VERS).zip
+DIST_NAME = z180-stamp-cpm3_$(VERS).zip
+DIST_NAME_BIN = z180-stamp-cpm3-bin_$(VERS).zip
+PREFIX = z180-stamp-cpm3_$(VERS)
+
+CP = cp
+RM = rm -f
+GIT = git
+ZIP = zip
 
 #CP/M emulator
 CPMEMU = zxcc
@@ -64,8 +71,6 @@ sys: $(SYSFILE)
 bios: bnkbios3.spr
 map: $(MAPFILE)
 
-.phony: bin-dist
-bin-dist: $(ZIPFILE)
 
 $(OBJ):  $(INC)
 boot.rel: version.inc
@@ -157,17 +162,25 @@ bnkbios3.spr : $(OBJ)
 	@$(cpm-asm)
 
 
-$(ZIPFILE): $(SYSFILE) $(MAPFILE)
-	@rm -f $@
-	zip -9 $@ $(SYSFILE) $(MAPFILE)
+.phony: bin-dist
+bin-dist: $(SYSFILE) $(MAPFILE)
+	$(ZIP) -9 $(DIST_NAME_BIN) $(SYSFILE) $(MAPFILE)
+
+.phony: dist
+dist: $(SYSFILE) $(MAPFILE)
+	$(GIT) archive --format=zip --prefix=$(PREFIX)/ -9 -o $(DIST_NAME) HEAD^{tree}
+	@mkdir -p $(PREFIX)
+	@$(CP) autorevision.cache version.inc $(PREFIX)
+	$(ZIP) -r -9 $(DIST_NAME) $(PREFIX) $(SYSFILE) $(MAPFILE)
+	@$(RM) -r $(PREFIX)
 
 
 .phony: clean realclean
 clean:
-	rm -f *.rel *.lst *.sym version.inc
+	$(RM) *.rel *.lst *.sym version.inc
 
 realclean: clean
-	rm -f *.map *.prn *~
+	$(RM) *.map *.prn *~
 
 
 #==================================================================
diff --git a/cbios/config.inc b/cbios/config.inc
deleted file mode 120000
index a046ba4..0000000
--- a/cbios/config.inc
+++ /dev/null
@@ -1 +0,0 @@
-../../z180-stamp/z180/config.inc
\ No newline at end of file
diff --git a/cbios/config.inc b/cbios/config.inc
new file mode 100644
index 0000000..4421478
--- /dev/null
+++ b/cbios/config.inc
@@ -0,0 +1,220 @@
+
+FALSE	equ	0
+TRUE	equ	NOT FALSE
+
+
+DEBUG	equ	true
+
+banked	equ	true
+
+;-----------------------------------------------------
+; CPU and BANKING types
+
+
+CPU_Z180	equ	TRUE
+CPU_Z80		equ	FALSE
+
+ROMSYS		equ	FALSE
+
+AVRCLK		equ	18432		;[KHz]
+
+    if CPU_Z180
+
+;-----------------------------------------------------
+;FOSC		equ	AVRCLK/2	;Oscillator frequency [KHz]
+;PHI		equ	FOSC*2		;CPU frequency (clock doubler enabled)
+
+;----------------------------------------------------------------------
+; Baudrate Generator for x16 clock mode:
+; TC = (f PHI / (32 * baudrate)) - 2
+;
+;     PHI [MHz]: 9.216 18.432
+;     baudrate     TC     TC
+;     ----------------------
+;      115200	    -      3
+;	57600	    3      8
+;	38400       -     13
+;	19200	   13     28
+;	 9600	   28     58
+
+
+;-----------------------------------------------------
+; Programmable Reload Timer (PRT)
+
+PRT_PRE		equ	20		;PRT prescaler
+
+;-----------------------------------------------------
+; MMU
+
+COMMON_SIZE	equ	4*1024		;Common Area size in bytes
+					;must be multiple of 4K
+if (COMMON_SIZE mod 1000h)
+	.printx COMMON_SIZE not multiple of 4K!
+	end	;stop assembly
+endif
+CMN_SIZE	equ	COMMON_SIZE/1000h		;4K units
+BNK_SIZE	equ	64/4 - CMN_SIZE			;bank size (4K units)
+BANKS		equ	(512/4 - CMN_SIZE)/BNK_SIZE	;max nr. of banks
+
+; Logical address space, CBAR values
+
+CA		equ	10h - CMN_SIZE		;common area start (64K - common size)
+BA		equ	0			;banked area start
+
+   if 0
+
+SYS$CBR		equ	0
+SYS$CBAR	equ	CA*16 + CA	;CBAR in system mode
+USR$CBAR	equ	CA*16 + BA	;CBAR in user mode (CP/M)
+
+   endif
+   if 1
+
+SYS$CBR		equ	BNK_SIZE
+SYS$CBAR	equ	CA*16 + CA	;CBAR in system mode
+USR$CBAR	equ	CA*16 + BA	;CBAR in user mode (CP/M)
+
+   endif
+
+
+;-----------------------------------------------------
+
+CREFSH		equ	0		;Refresh rate register (disable refresh)
+CWAITIO		equ	3 shl IWI0	;Max I/O Wait States, 0 Memory Wait States
+PHI_X2		equ	0		;set to M_X2CM to enable the clock doubler
+
+    endif 		;CPU_Z180
+    if	CPU_Z80
+
+PHI		equ	AVRCLK/5	;CPU frequency [KHz]
+BAUDCLCK	equ	AVRCLK/10	;Baudrate clock [KHz]
+;BDCLK16		equ
+
+SIOAD	EQU	0bch
+SIOAC	EQU	0bdh
+SIOBD	EQU	0beh
+SIOBC	EQU	0bfh
+
+CTC0	EQU	0f4h
+CTC1	EQU	0f5h
+CTC2	EQU	0f6h
+CTC3	EQU	0f7h
+
+;
+; Init Serial I/O for console input and output (SIO-A)
+;
+; Baudrate clock: 1843200 Hz (Bus connector pin A17)
+;
+; Baudrate   Divider	SIO	CTC
+; ---------------------------------
+; 115200	  16	 16	  1
+;  57600	  32	 16	  2
+;  38400	  48	 16	  3
+;  19200	  96	 16	  6
+;   9600	 192	 16	 12
+;   4800	 384	 16	 24
+;   2400	 768	 16	 48
+;   1200	1536	 16	 96
+;    600	3072	 16	192
+;    300	6144	 64	 92
+
+    endif	; CPU_Z80
+
+    if	ROMSYS
+c$rom		equ	0a5h
+ROM_EN		equ	0C0h
+ROM_DIS		equ	ROMEN+1
+     if CPU_Z180
+CWAITROM 	equ	2 shl MWI0
+     endif
+    endif
+
+
+DDTZRSTVEC 	equ	030h		;DDTZ Restart vector (breakpoints)
+
+INIDONE		equ	03Fh		;CP/M skip hw init, if this address
+INIDONEVAL	equ	080h		;    is set to this value.
+
+mtx.fifo_len	equ	64		;Message transfer fifos
+mtx.fifo_id	equ	0		;    This *must* have #0
+mrx.fifo_len	equ	64
+mrx.fifo_id	equ	1
+
+ci.fifo_len	equ	32		;AVRCON (USB0) Character I/O via AVR
+ci.fifo_id	equ	2
+co.fifo_len	equ	32
+co.fifo_id	equ	3
+
+s0.rx_len	equ	128		;Serial 0 (ASCI0) buffers
+s0.rx_id	equ	4		;
+s0.tx_len	equ	128		;
+s0.tx_id	equ	5		;
+
+s1.rx_len	equ	128		;Serial 1 (ASCI1) buffers
+s1.rx_id	equ	6		;
+s1.tx_len	equ	128		;
+s1.tx_id	equ	7		;
+
+AVRINT5		equ	4Fh
+AVRINT6		equ	5Fh
+;PMSG		equ	80h
+
+;-----------------------------------------------------
+; Definition of (logical) top 2 memory pages
+
+sysram_start	equ	0FE00h
+bs$stack$size	equ	80
+
+isvsw_loc	equ	0FEE0h
+
+ivtab		equ	0ffc0h		;int vector table
+iv2tab		equ	ivtab + 2*9
+
+
+
+;-----------------------------------------------------
+
+o.id		equ	-4
+o.mask		equ	-3
+o.in_idx	equ	-2
+o.out_idx	equ	-1
+
+	.lall
+
+mkbuf	macro	id,name,size
+  if ((size AND (size-1)) NE 0) OR (size GT 256)
+    .printx Error: buffer ^size must be power of 2 and in range 0..256!
+    name&.mask equ ;wrong size error
+  else
+    db id
+    db size-1
+    ds 2
+    name:: ds size
+    name&.mask equ low (size-1)
+    if size ne 0
+      name&.end equ $-1
+      name&.len equ size
+      name&.id equ id
+    endif
+  endif
+endm
+
+;-----------------------------------------------------
+
+inidat	macro
+	cseg
+??ps.a	defl	$
+	endm
+
+inidate	macro
+??ps.len defl	$ - ??ps.a
+	dseg
+	ds	??ps.len
+	endm
+
+;-----------------------------------------------------
+
+b0call	macro	address
+	call	_b0call
+	dw	address
+	endm
diff --git a/cbios/z180reg.inc b/cbios/z180reg.inc
deleted file mode 120000
index 01c2a6b..0000000
--- a/cbios/z180reg.inc
+++ /dev/null
@@ -1 +0,0 @@
-../../z180-stamp/z180/z180reg.inc
\ No newline at end of file
diff --git a/cbios/z180reg.inc b/cbios/z180reg.inc
new file mode 100644
index 0000000..2666867
--- /dev/null
+++ b/cbios/z180reg.inc
@@ -0,0 +1,197 @@
+	.xlist
+
+;;
+;; HD64180/Z180 Register Definitions
+;;
+
+
+b2m	macro	name,nr
+name	equ	nr
+M_&name	equ	1 shl nr
+	endm
+
+;	ifndef	IOBASE
+IOBASE	equ	0
+;	endif
+
+cntla0	equ	IOBASE+00h	;ASCI Control Register A Channel 0
+cntla1	equ	IOBASE+01h	;ASCI Control Register A Channel 1
+	b2m MPE, 7		;Multi-Processor Mode Enable
+	b2m RE, 6		;Receiver Enable
+	b2m TE, 5		;Transmitter Enable
+	b2m RTS0, 4		;Request to Send Channel 0
+	b2m CKA1D, 4		;
+	b2m MPBR, 3		;Multiprocessor Bit Receive (Read)
+	b2m EFR, 3		;Error Flag Reset (Write)
+	b2m MOD2, 2		;Data Format Mode 1 = 8-Bit data
+	b2m MOD1, 1		;1 = Parity enabled
+	b2m MOD0, 0		;1 = 2 stop bits
+
+cntlb0	equ	IOBASE+02h	;ASCI Control Register B Channel 0
+cntlb1	equ	IOBASE+03h	;ASCI Control Register B Channel 1
+	b2m MPBT,7		;Multiprocessor Bit Transmit
+	b2m MP,6		;Multiprocessor Mode
+	b2m CTS,5		;Clear to Send
+	b2m PS,5		;Prescale
+	b2m PEO,4		;Parity Even Odd
+	b2m DR,3		;Divede Ratio
+	b2m SS2,2		;Source/Speed Select 2,1,0
+	b2m SS1,1		;
+	b2m SS0,0		;
+
+stat0	equ	IOBASE+04h	;ASCI Status Channel 0
+stat1	equ	IOBASE+05h	;ASCI Status Channel 1
+	b2m RDRF,7		;Receive Data Register Full
+	b2m OVRN,6		;Overrun Error
+	b2m PERR,5		;Parity Error   (M80: PE conflicts with JP/CALL cc)
+	b2m FE,4		;Framing Error
+	b2m RIE,3		;Receive Interrupt Enable
+	b2m DCD0,2		;Data Carrier Detect (Ch 0)
+	b2m CTS1E,2		;Clear To Send (Ch 1)
+	b2m TDRE,1		;Transmit Data Register Empty
+	b2m TIE,0		;Transmit Interrupt Enable
+
+tdr0	equ	IOBASE+06h	;ASCI Transmit Data
+tdr1	equ	IOBASE+07h	;ASCI Transmit Data
+rdr0	equ	IOBASE+08h	;ASCI Receive Data
+rdr1	equ	IOBASE+09h	;ASCI Receive Data
+
+cntr	equ	IOBASE+0Ah	;CSI/O Control Register
+trdr	equ	IOBASE+0Bh	;CSI/O Transmit/Receive Data Register
+
+tmdr0l	equ	IOBASE+0Ch	;Timer Data Register Channel 0
+tmdr0h	equ	IOBASE+0Dh	;
+rldr0l	equ	IOBASE+0Eh	;Timer Reload Register Channel 0
+rldr0h	equ	IOBASE+0Fh	;
+tcr	equ	IOBASE+10h	;Timer Control Register
+	b2m TIF1,7		;Timer Interrupt Flag
+	b2m TIF0,6		;
+	b2m TIE1,5		;Timer Interrupt Enable
+	b2m TIE0,4		;
+	b2m TOC1,3		;Timer Output Control
+	b2m TOC0,2		;
+	b2m TDE1,1		;Timer Down Count Enable
+	b2m TDE0,0		;
+
+
+asext0	equ	IOBASE+12h	;ASCI Extension Control Register
+asext1	equ	IOBASE+13h	;ASCI Extension Control Register
+	b2m DCD0DIS,6		;DCD0 Disable
+	b2m CTS0DIS,5		;CTS0 Disable
+	b2m X1,4		;CKA * 1 Clock/Samle Rate Divider
+	b2m BRGMOD,3		;BRG Mode (Baud rate generator)
+	b2m BREAKEN,2		;Break Enable
+	b2m BREAK,1		;Break detected
+	b2m SENDBREAK,0		;Send Break
+
+tmdr1l	equ	IOBASE+14h	;Timer Data Register Channel 1
+tmdr1h	equ	IOBASE+15h	;
+rldr1l	equ	IOBASE+16h	;Timer Reload Register Channel 1
+rldr1h	equ	IOBASE+17h	;
+
+frc	equ	IOBASE+18h	;Free Running Counter
+
+astc0l	equ	IOBASE+1Ah	;ASCI Time Constant Register 0
+astc0h	equ	IOBASE+1Bh	;
+astc1l	equ	IOBASE+1Ch	;ASCI Time Constant Register 1
+astc1h	equ	IOBASE+1Dh	;
+
+cmr	equ	IOBASE+1Eh	;Clock Mutiplier Register
+	b2m X2CM,7		;X2 Clock Multiplier
+	b2m LNC,6		;Low Noise Crystal
+
+ccr	equ	IOBASE+1Fh	;CPU Control Register
+	b2m NCD	7		;No Clock Divide
+
+sar0l	equ	IOBASE+20h	;DMA Src Adr Register Channel 0
+sar0h	equ	IOBASE+21h	;
+sar0b	equ	IOBASE+22h	;
+dar0l	equ	IOBASE+23h	;DMA Dst Adr Register Channel 0
+dar0h	equ	IOBASE+24h	;
+dar0b	equ	IOBASE+25h	;
+bcr0l	equ	IOBASE+26h	;DMA Byte Count Register Channel 0
+bcr0h	equ	IOBASE+27h	;
+
+mar1l	equ	IOBASE+28h	;DMA Memory Address Register Channel 1
+mar1h	equ	IOBASE+29h	;
+mar1b	equ	IOBASE+2Ah	;
+iar1l	equ	IOBASE+2Bh	;DMA I/O Address Register Channel 1
+iar1h	equ	IOBASE+2Ch	;
+iar1b	equ	IOBASE+2Dh	;
+	b2m ALTE,7		;Alternating Chnnels
+	b2m ALTC,6		;Currently selected DMA Channel when Bit7=1
+	b2m REQ1SEL2,2		;
+	b2m REQ1SEL1,1		;
+	b2m REQ1SEL0,0		;
+
+bcr1l	equ	IOBASE+2Eh	;DMA Byte Count Register Channel 1
+bcr1h	equ	IOBASE+2Fh	;
+
+dstat	equ	IOBASE+30h	;DMA Status Register
+	b2m DE1,7		;DMA enable ch 1,0
+	b2m DE0,6		;
+	b2m NDWE1,5		;DMA Enable Bit Write Enable 1,0
+	b2m NDWE0,4		;
+	b2m DIE1,3		;DMA Interrupt Enable 1,0
+	b2m DIE0,2		;
+	b2m DME,0		;DMA Master enable
+
+dmode	equ	IOBASE+31h	;DMA Mode Register
+	b2m DM1,5		;Ch 0 Destination Mode 1,0
+	b2m DM0,4		;
+	b2m SM1,3		;Ch 0 Source Mode 1,0
+	b2m SM0,2		;
+	b2m MMOD,1		;Memory MODE select (0=cycle steel/1=burst)
+
+dcntl	equ	IOBASE+32h	;DMA/WAIT Control
+	b2m MWI1,7		;Memory Wait Insertion
+	b2m MWI0,6		;
+	b2m IWI1,5		;I/O Wait Insertion
+	b2m IWI0,4		;
+	b2m DMS1,3		;DREQi Select (Edge/Level)
+	b2m DMS0,2		;
+	b2m DIMA1,1		;DMA Ch1 I/O Memory Mode Select
+	b2m DIMA0,0
+M_MWI	equ M_MWI1 + M_MWI0
+M_IWI	equ M_IWI1 + M_IWI0
+
+il	equ 	IOBASE+33h	;Interrupt Vector Low Register
+itc	equ	IOBASE+34h	;INT/TRAP Control Register
+	b2m TRAP,7		;Trap
+	b2m UFO,6		;Unidentified Fetch Object
+	b2m ITE2,2		;/INT Enable 2,1,0
+	b2m ITE1,1		;
+	b2m ITE0,0		;
+
+rcr	equ	IOBASE+36h	;Refresh Control Register
+	b2m REFE,7		;Refresh Enable
+	b2m REFW,6		;Refresh Wait State
+	b2m CYC1,1		;Cycle select
+	b2m CYC0,0		;
+
+cbr	equ	IOBASE+38h	;MMU Common Base Register
+bbr	equ	IOBASE+39h	;MMU Bank Base Register
+cbar	equ	IOBASE+3Ah	;MMU Common/Bank Register
+
+omcr	equ	IOBASE+3Eh	;Operation Mode Control Register
+	b2m M1E,7		;M1 Enable
+	b2m M1TE,6		;M1 Temporary Enable
+	b2m IOC,5		;I/O Compatibility
+
+icr	equ	IOBASE+3Fh	;I/O Control Register
+	b2m IOSTP,5		;I/O Stop
+;
+; Interrupt Vectors
+;
+
+IV$INT1	 equ	0		;/INT1         (highest priority)
+IV$INT2	 equ	2		;/INT2
+IV$PRT0	 equ	4		;PRT channel 0
+IV$PRT1	 equ	6		;PRT channel 1
+IV$DMA0	 equ	8		;DMA channel 0
+IV$DMA1	 equ	10		;DMA channel 1
+IV$CSIO	 equ	12		;CSI/O
+IV$ASCI0 equ	14		;ASCI channel 0
+IV$ASCI1 equ	16		;ASCI channel 1 (lowest priority)
+
+	.list