]>
Commit | Line | Data |
---|---|---|
7f552300 L |
1 | /*-----------------------------------------------------------------------*/ |
2 | /* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2007 */ | |
3 | /*-----------------------------------------------------------------------*/ | |
4 | /* Only spi_rcvr(), spi_xmit(), disk_timerproc() and some macros */ | |
5 | /* are platform dependent. */ | |
6 | /*-----------------------------------------------------------------------*/ | |
7 | ||
f82d019d | 8 | #include "common.h" |
7f552300 L |
9 | #include <stdbool.h> |
10 | #include "timer.h" | |
11 | #include "spi.h" | |
12 | #include "diskio.h" | |
a870134a | 13 | #include "debug.h" |
7f552300 | 14 | |
1222f338 | 15 | #define MAX_DRV 2 |
7f552300 | 16 | |
f82d019d L |
17 | /* Port Controls (Platform dependent) */ |
18 | /* SD card socket connections */ | |
19 | ||
15e476bc L |
20 | /* TODO: config.h cofig macros */ |
21 | ||
22 | //#define SD_CD_0 SBIT(PORT,) /* Card detect switch */ | |
1222f338 L |
23 | //#define SD_CD_0_IN SBIT(PIN,) |
24 | //#define SD_CD_0_DDR SBIT(DDR,) | |
25 | ||
15e476bc | 26 | //#define SD_WP_0 SBIT(PORT,) /* Write protect switch */ |
1222f338 L |
27 | //#define SD_WP_0_IN SBIT(PIN,) |
28 | //#define SD_WP_0_DDR SBIT(DDR,) | |
29 | ||
15e476bc | 30 | #define SD_CS_0 SBIT(PORTB,0) /* Chip select pin */ |
1222f338 L |
31 | #define SD_CS_0_IN SBIT(PINB,0) |
32 | #define SD_CS_0_DDR SBIT(DDRB,0) | |
33 | ||
15e476bc L |
34 | |
35 | //#define SD_CD_1 SBIT(PORTG,3) /* Card detect switch */ | |
8b6edd92 L |
36 | //#define SD_CD_1_IN SBIT(PING,3) |
37 | //#define SD_CD_1_DDR SBIT(DDRG,3) | |
f82d019d | 38 | |
15e476bc L |
39 | //#define SD_WP_1 SBIT(PORTG,5) /* Write protect switch */ |
40 | //#define SD_WP_1_IN SBIT(PING,5) | |
41 | //#define SD_WP_1_DDR SBIT(DDRG,5) | |
f82d019d L |
42 | |
43 | #define SD_CS_1 SBIT(PORTG,4) /* Chip select pin */ | |
44 | #define SD_CS_1_IN SBIT(PING,4) | |
45 | #define SD_CS_1_DDR SBIT(DDRG,4) | |
46 | ||
47 | ||
a870134a | 48 | #define SPI_CLK_SLOW() SPISetMMCInitClock() /* Set slow clock (100k-400k) */ |
15e476bc | 49 | #define SPI_CLK_FAST() SPISetFastClock() /* Set fast clock (depends on the CSD) */ |
f82d019d L |
50 | |
51 | /*-------------------------------------------------------------------------- | |
52 | Definitions for MMC/SDC command | |
53 | ---------------------------------------------------------------------------*/ | |
54 | ||
7f552300 L |
55 | #define CMD0 (0) /* GO_IDLE_STATE */ |
56 | #define CMD1 (1) /* SEND_OP_COND (MMC) */ | |
57 | #define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */ | |
58 | #define CMD8 (8) /* SEND_IF_COND */ | |
59 | #define CMD9 (9) /* SEND_CSD */ | |
60 | #define CMD10 (10) /* SEND_CID */ | |
61 | #define CMD12 (12) /* STOP_TRANSMISSION */ | |
62 | #define ACMD13 (0x80+13) /* SD_STATUS (SDC) */ | |
63 | #define CMD16 (16) /* SET_BLOCKLEN */ | |
64 | #define CMD17 (17) /* READ_SINGLE_BLOCK */ | |
65 | #define CMD18 (18) /* READ_MULTIPLE_BLOCK */ | |
66 | #define CMD23 (23) /* SET_BLOCK_COUNT (MMC) */ | |
67 | #define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ | |
68 | #define CMD24 (24) /* WRITE_BLOCK */ | |
69 | #define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ | |
70 | #define CMD55 (55) /* APP_CMD */ | |
71 | #define CMD58 (58) /* READ_OCR */ | |
72 | ||
73 | ||
7f552300 L |
74 | /*-------------------------------------------------------------------------- |
75 | ||
76 | Module Private Functions | |
77 | ||
78 | ---------------------------------------------------------------------------*/ | |
79 | ||
f82d019d L |
80 | struct sdsock_stat_s { |
81 | volatile DSTATUS stat; /* Disk/socket status */ | |
82 | BYTE CardType; /* Card type flags */ | |
83 | }; | |
7f552300 L |
84 | |
85 | static | |
f82d019d | 86 | struct sdsock_stat_s |
1222f338 | 87 | socket[MAX_DRV] = { |
f82d019d L |
88 | {.stat=STA_NOINIT}, |
89 | {.stat=STA_NOINIT} | |
90 | }; | |
7f552300 L |
91 | |
92 | /*-----------------------------------------------------------------------*/ | |
93 | /* Wait for card ready */ | |
94 | /*-----------------------------------------------------------------------*/ | |
95 | ||
96 | static | |
97 | int wait_ready (void) /* 1:OK, 0:Timeout */ | |
98 | { | |
99 | uint32_t to = get_timer(0); | |
100 | ||
101 | /* Wait for ready in timeout of 500ms */ | |
102 | do { | |
103 | if (spi_rcvr() == 0xFF) { | |
104 | return 1; | |
105 | } | |
106 | } while (get_timer(to) < 500); | |
107 | ||
108 | return 0; | |
109 | } | |
110 | ||
111 | /*-----------------------------------------------------------------------*/ | |
112 | /* Deselect the card and release SPI bus */ | |
113 | /*-----------------------------------------------------------------------*/ | |
114 | ||
115 | static | |
1222f338 | 116 | void deselect(BYTE drv) |
7f552300 | 117 | { |
8b6edd92 | 118 | //debug("*** enter deselect()\n"); |
1222f338 L |
119 | if (drv == 0) |
120 | SD_CS_0 = 1; | |
a870134a | 121 | else { |
1222f338 | 122 | SD_CS_1 = 1; |
a870134a L |
123 | } |
124 | ||
7f552300 | 125 | /* Dummy clock (TODO: force DO hi-z for multiple slave SPI) */ |
a870134a L |
126 | if (socket[drv].stat & STA_FAST) |
127 | SPI_CLK_FAST(); | |
128 | else | |
129 | SPI_CLK_SLOW(); | |
7f552300 | 130 | spi_rcvr(); |
a870134a L |
131 | SPI_OFF(); |
132 | ||
133 | if (drv == 0) { | |
2fe28316 L |
134 | #ifdef SD_CS_0_IN |
135 | SD_CS_0_DDR = 0; | |
136 | SD_CS_0 = 0; | |
a870134a L |
137 | #endif |
138 | } else { | |
2fe28316 | 139 | #ifdef SD_CS_1_IN |
a870134a L |
140 | SD_CS_1_DDR = 0; |
141 | SD_CS_1 = 0; | |
142 | #endif | |
143 | } | |
8b6edd92 | 144 | //debug("*** exit deselect()\n"); |
7f552300 L |
145 | } |
146 | ||
7f552300 L |
147 | /*-----------------------------------------------------------------------*/ |
148 | /* Select the card and wait for ready */ | |
149 | /*-----------------------------------------------------------------------*/ | |
150 | ||
151 | static | |
1222f338 | 152 | int select(BYTE drv) /* 1:Successful, 0:Timeout */ |
7f552300 | 153 | { |
8b6edd92 | 154 | //debug("*** enter select()\n"); |
2fe28316 L |
155 | if (drv == 0) { |
156 | #ifdef SD_CS_0_IN | |
157 | SD_CS_0 = 1; | |
158 | SD_CS_0_DDR = 1; | |
159 | #endif | |
1222f338 | 160 | SD_CS_0 = 0; |
2fe28316 L |
161 | } else { |
162 | #ifdef SD_CS_1_IN | |
a870134a L |
163 | SD_CS_1 = 1; |
164 | SD_CS_1_DDR = 1; | |
165 | #endif | |
1222f338 | 166 | SD_CS_1 = 0; |
a870134a L |
167 | } |
168 | ||
169 | if (socket[drv].stat & STA_FAST) | |
170 | SPI_CLK_FAST(); | |
171 | else | |
172 | SPI_CLK_SLOW(); | |
173 | ||
7f552300 L |
174 | /* Dummy clock (force DO enabled) */ |
175 | spi_rcvr(); | |
176 | ||
177 | if (wait_ready()) { | |
8b6edd92 | 178 | //debug("*** exit select() == 1\n"); |
7f552300 L |
179 | return 1; /* OK */ |
180 | } | |
1222f338 | 181 | deselect(drv); |
8b6edd92 | 182 | //debug("*** exit select() == 0\n"); |
7f552300 L |
183 | |
184 | return 0; /* Timeout */ | |
185 | } | |
186 | ||
187 | /*-----------------------------------------------------------------------*/ | |
188 | /* Power Control (Platform dependent) */ | |
189 | /*-----------------------------------------------------------------------*/ | |
190 | /* When the target system does not support socket power control, there */ | |
191 | /* is nothing to do in these functions and chk_power always returns 1. */ | |
192 | ||
193 | static | |
1222f338 | 194 | void power_on(BYTE drv) |
7f552300 | 195 | { |
8b6edd92 | 196 | //debug("*** enter power_on()\n"); |
7f552300 | 197 | |
1222f338 L |
198 | if (drv == 0) { |
199 | #ifdef SD_PWR_0 | |
1222f338 | 200 | SD_PWR_0 = 0; /* Drives PWR pin high */ |
1222f338 L |
201 | #endif |
202 | ||
1222f338 | 203 | } else { |
f82d019d | 204 | #ifdef SD_PWR_1 |
1222f338 | 205 | SD_PWR_1 = 0; /* Drives PWR pin high */ |
15e476bc L |
206 | #endif |
207 | } | |
208 | #if defined SD_PWR_0 || defined SD_PWR_1 | |
1222f338 L |
209 | for (uint32_t to = get_timer(0); get_timer(to) < 30;) |
210 | ; /* Wait for 30ms */ | |
7f552300 | 211 | #endif |
8b6edd92 | 212 | //debug("*** exit power_on()\n"); |
7f552300 L |
213 | } |
214 | ||
215 | static | |
1222f338 | 216 | void power_off(BYTE drv) |
7f552300 | 217 | { |
8b6edd92 | 218 | //debug("*** enter power_off()\n"); |
1222f338 L |
219 | select(drv); /* Wait for card ready */ |
220 | deselect(drv); | |
7f552300 | 221 | |
1222f338 L |
222 | if (drv == 0) { |
223 | #ifdef SD_PWR_0 | |
224 | SD_PWR_0 = 1; /* Socket power OFF */ | |
225 | #endif | |
226 | } else { | |
f82d019d | 227 | #ifdef SD_PWR_1 |
1222f338 | 228 | SD_PWR_1 = 1; /* Socket power OFF */ |
7f552300 | 229 | #endif |
1222f338 L |
230 | } |
231 | socket[drv].stat |= STA_NOINIT; | |
8b6edd92 | 232 | //debug("*** exit power_off()\n"); |
7f552300 L |
233 | } |
234 | ||
235 | #if 0 | |
236 | static | |
1222f338 | 237 | int chk_power(BYTE drv) /* Socket power state: 0=off, 1=on */ |
7f552300 | 238 | { |
1222f338 L |
239 | if (drv == 0) { |
240 | #ifdef SD_PWR_0 | |
241 | return SD_PWR_0 == 0; | |
242 | #else | |
243 | return 1; | |
244 | #endif /* SD_PWR_PIN */ | |
245 | } else { | |
f82d019d | 246 | #ifdef SD_PWR_1 |
1222f338 | 247 | return SD_PWR_1 == 0; |
7f552300 | 248 | #else |
1222f338 | 249 | return 1; |
7f552300 | 250 | #endif /* SD_PWR_PIN */ |
1222f338 | 251 | } |
7f552300 L |
252 | } |
253 | #endif | |
254 | ||
255 | /*-----------------------------------------------------------------------*/ | |
256 | /* Receive a data packet from MMC */ | |
257 | /*-----------------------------------------------------------------------*/ | |
258 | ||
259 | static | |
260 | int rcvr_datablock ( | |
261 | BYTE *buff, /* Data buffer to store received data */ | |
262 | UINT btr /* Byte count (must be multiple of 4) */ | |
263 | ) { | |
264 | BYTE token, tmp; | |
265 | uint32_t to = get_timer(0); | |
266 | ||
267 | /* Wait for data packet in timeout of 200ms */ | |
268 | do { | |
269 | token = spi_rcvr(); | |
270 | } while ((token == 0xFF) && get_timer(to) < 200); | |
271 | if(token != 0xFE) return 0; /* If not valid data token, retutn with error */ | |
272 | ||
273 | tmp = spi_rcvr(); /* shift in first byte */ | |
274 | spi_write(0xff); /* start shift in next byte */ | |
275 | while (--btr) { | |
276 | *buff++ = tmp; | |
277 | asm volatile (""::"r"(buff), "r"(btr)); | |
278 | spi_wait(); | |
279 | tmp = SPDR; | |
280 | spi_write(0xff); | |
281 | } | |
282 | *buff = tmp; /* store last byte in buffer while SPI module shifts in crc part1 */ | |
283 | spi_wait(); | |
284 | spi_rcvr(); /* second crc */ | |
285 | ||
286 | return 1; /* Return with success */ | |
287 | } | |
288 | ||
289 | /*-----------------------------------------------------------------------*/ | |
290 | /* Send a data packet to MMC */ | |
291 | /*-----------------------------------------------------------------------*/ | |
292 | ||
293 | #if _USE_WRITE | |
294 | static | |
295 | int xmit_datablock ( | |
296 | const BYTE *buff, /* 512 byte data block to be transmitted */ | |
297 | BYTE token /* Data/Stop token */ | |
298 | ) | |
299 | { | |
300 | BYTE resp, tmp; | |
301 | UINT btr; | |
302 | ||
303 | if (!wait_ready()) return 0; | |
304 | ||
305 | spi_write(token); /* Xmit data token */ | |
306 | if (token != 0xFD) { /* Is data token */ | |
307 | btr = 512; | |
308 | do { | |
309 | tmp = *buff++; | |
310 | spi_wait(); | |
311 | spi_write(tmp); | |
312 | }while (--btr); | |
313 | spi_wait(); | |
314 | spi_xmit(0xff); /* CRC (Dummy) */ | |
315 | spi_xmit(0xff); | |
316 | resp = spi_rcvr(); /* Reveive data response */ | |
317 | return ((resp & 0x1F) != 0x05) ? 0 : 1; /* If not accepted, return with error */ | |
318 | } | |
319 | ||
320 | spi_wait(); | |
321 | return 1; | |
322 | } | |
323 | #endif /* _USE_WRITE */ | |
324 | ||
325 | /*-----------------------------------------------------------------------*/ | |
326 | /* Send a command packet to MMC */ | |
327 | /*-----------------------------------------------------------------------*/ | |
328 | ||
329 | static | |
330 | BYTE send_cmd ( /* Returns R1 resp (bit7==1:Send failed) */ | |
1222f338 L |
331 | BYTE drv, /* Physical drive nmuber (0) */ |
332 | BYTE cmd, /* Command index */ | |
333 | DWORD arg /* Argument */ | |
7f552300 L |
334 | ) { |
335 | union { | |
336 | DWORD as32; | |
337 | BYTE as8[4]; | |
338 | } argtmp; | |
339 | BYTE n, res; | |
340 | ||
8b6edd92 | 341 | //debug("*** send_cmd( %.2x )\n", cmd); |
7f552300 L |
342 | |
343 | if (cmd & 0x80) { /* ACMD<n> is the command sequense of CMD55-CMD<n> */ | |
344 | cmd &= 0x7F; | |
1222f338 | 345 | res = send_cmd(drv, CMD55, 0); |
7f552300 L |
346 | if (res > 1) |
347 | return res; | |
348 | } | |
349 | ||
350 | /* Select the card and wait for ready except to stop multiple block read */ | |
351 | if (cmd != CMD12) { | |
1222f338 L |
352 | deselect(drv); |
353 | if (!select(drv)) | |
7f552300 L |
354 | return 0xFF; |
355 | } | |
356 | ||
357 | /* Send command packet */ | |
358 | spi_xmit(0x40 | cmd); /* Start + Command index */ | |
359 | argtmp.as32 = arg; | |
360 | spi_xmit(argtmp.as8[3]); /* Argument[31..24] */ | |
361 | spi_xmit(argtmp.as8[2]); /* Argument[23..16] */ | |
362 | spi_xmit(argtmp.as8[1]); /* Argument[15..8] */ | |
363 | spi_xmit(argtmp.as8[0]); /* Argument[7..0] */ | |
364 | ||
365 | n = 0x01; /* Dummy CRC + Stop */ | |
366 | if (cmd == CMD0) | |
367 | n = 0x95; /* Valid CRC for CMD0(0) */ | |
368 | if (cmd == CMD8) | |
369 | n = 0x87; /* Valid CRC for CMD8(0x1AA) */ | |
370 | spi_xmit(n); | |
371 | ||
372 | /* Receive command response */ | |
373 | if (cmd == CMD12) | |
374 | spi_rcvr(); /* Skip a stuff byte when stop reading */ | |
375 | n = 10; /* Wait for a valid response in timeout of 10 attempts */ | |
376 | do | |
377 | res = spi_rcvr(); | |
378 | while ((res & 0x80) && --n); | |
379 | ||
380 | return res; /* Return with the response value */ | |
381 | } | |
382 | ||
383 | /*-------------------------------------------------------------------------- | |
384 | ||
385 | Public Functions | |
386 | ||
387 | ---------------------------------------------------------------------------*/ | |
388 | ||
15e476bc L |
389 | void setup_mmc(void) |
390 | { | |
391 | #ifdef SD_PWR_0 | |
392 | SD_PWR_1 = 1; /* Drives PWR pin low */ | |
393 | SD_PWR_0_DDR = 1; /* Turns on PWR pin as output */ | |
394 | #endif | |
395 | #ifdef SD_WP_0 | |
396 | SD_WP_0_DDR = 0; | |
397 | SD_WP_0 = 1; /* Pullup */ | |
398 | #endif | |
399 | ||
400 | #ifdef SD_PWR_1 | |
401 | SD_PWR_1 = 1; /* Drives PWR pin low */ | |
402 | SD_PWR_1_DDR = 1; /* Turns on PWR pin as output */ | |
403 | #endif | |
404 | #ifdef SD_WP_1 | |
405 | SD_WP_1_DDR = 0; | |
406 | SD_WP_1 = 1; /* Pullup */ | |
407 | #endif | |
408 | ||
409 | /* SPI as master */ | |
410 | PRR0 &= ~_BV(PRSPI); | |
411 | SPI_DDR = (SPI_DDR & ~(_BV(SPI_MISO) | _BV(SPI_SS))) | |
412 | | _BV(SPI_MOSI) | _BV(SPI_SCK); | |
413 | SPI_PORT = SPI_PORT & ~(_BV(SPI_MOSI) | _BV(SPI_SCK)); | |
414 | ||
415 | #if defined SD_CD_0 | |
416 | SD_CD_0_DDR = 0; | |
417 | SD_CD_0 = 1; | |
418 | #elif defined SD_CS_0_IN | |
419 | SD_CS_0_DDR = 0; | |
420 | SD_CS_0 = 0; | |
421 | #else | |
422 | SD_CS_0_DDR = 1; | |
423 | SD_CS_0 = 1; | |
424 | #endif | |
425 | ||
426 | #if defined SD_CD_1 | |
427 | SD_CD_1_DDR = 0; | |
428 | SD_CD_1 = 1; | |
429 | #elif defined SD_CS_1_IN | |
430 | SD_CS_1_DDR = 0; | |
431 | SD_CS_1 = 0; | |
432 | #else | |
433 | SD_CS_1_DDR = 1; | |
434 | SD_CS_1 = 1; | |
435 | #endif | |
436 | } | |
437 | ||
7f552300 L |
438 | /*-----------------------------------------------------------------------*/ |
439 | /* Initialize Disk Drive */ | |
440 | /*-----------------------------------------------------------------------*/ | |
441 | ||
442 | #define MMC_INIT_TO 1000 /* 1s */ | |
443 | ||
444 | DSTATUS disk_initialize ( | |
445 | BYTE drv /* Physical drive nmuber (0) */ | |
446 | ) | |
447 | { | |
448 | BYTE n, cmd, ty, ocr[4]; | |
449 | ||
1222f338 | 450 | if (drv >= MAX_DRV) |
7f552300 | 451 | return STA_NOINIT; /* Supports only single drive */ |
f82d019d | 452 | if (socket[drv].stat & STA_NODISK) |
11b53d3f | 453 | return socket[drv].stat & STAT_MASK; /* No card in the socket */ |
7f552300 | 454 | |
1222f338 | 455 | power_on(drv); /* Force socket power on */ |
a870134a L |
456 | socket[drv].stat &= ~STA_FAST; |
457 | SPI_CLK_SLOW(); | |
7f552300 L |
458 | for (n = 10; n; n--) |
459 | spi_rcvr(); /* 80 dummy clocks */ | |
460 | ||
461 | ty = 0; | |
1222f338 | 462 | if (send_cmd(drv, CMD0, 0) == 1) { /* Enter Idle state */ |
7f552300 L |
463 | /* Init timeout timer */ |
464 | uint32_t timer = get_timer(0); | |
465 | ||
1222f338 L |
466 | if (send_cmd(drv, CMD8, 0x1AA) == 1) { /* SDv2? */ |
467 | /* Get trailing return value of R7 resp */ | |
468 | for (n = 0; n < 4; n++) | |
469 | ocr[n] = spi_rcvr(); | |
470 | if (ocr[2] == 0x01 && ocr[3] == 0xAA) { | |
471 | /* The card can work at vdd range of 2.7-3.6V */ | |
472 | while (get_timer(timer) < MMC_INIT_TO | |
473 | && send_cmd(drv, ACMD41, 1UL << 30)) | |
474 | ; /* Wait for leaving idle state (ACMD41 with HCS bit) */ | |
475 | if (get_timer(timer) < MMC_INIT_TO && send_cmd(drv, CMD58, 0) == 0) { | |
476 | /* Check CCS bit in the OCR */ | |
477 | for (n = 0; n < 4; n++) | |
478 | ocr[n] = spi_rcvr(); | |
7f552300 L |
479 | ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* SDv2 */ |
480 | } | |
481 | } | |
482 | } else { /* SDv1 or MMCv3 */ | |
1222f338 | 483 | if (send_cmd(drv, ACMD41, 0) <= 1) { |
7f552300 L |
484 | ty = CT_SD1; cmd = ACMD41; /* SDv1 */ |
485 | } else { | |
486 | ty = CT_MMC; cmd = CMD1; /* MMCv3 */ | |
487 | } | |
488 | ||
489 | /* Wait for leaving idle state */ | |
1222f338 L |
490 | while (get_timer(timer) < MMC_INIT_TO && send_cmd(drv, cmd, 0)) |
491 | ; | |
7f552300 L |
492 | |
493 | /* Set R/W block length to 512 */ | |
1222f338 | 494 | if (!(get_timer(timer) < MMC_INIT_TO) || send_cmd(drv, CMD16, 512) != 0) |
7f552300 L |
495 | ty = 0; |
496 | } | |
497 | } | |
f82d019d | 498 | socket[drv].CardType = ty; |
1222f338 | 499 | deselect(drv); |
7f552300 L |
500 | |
501 | if (ty) { /* Initialization succeded */ | |
8b6edd92 L |
502 | /* Clear STA_NOINIT */ |
503 | socket[drv].stat = (socket[drv].stat & ~STA_NOINIT) | STA_FAST; | |
7f552300 | 504 | } else { /* Initialization failed */ |
1222f338 | 505 | power_off(drv); |
7f552300 L |
506 | } |
507 | ||
11b53d3f | 508 | return socket[drv].stat & STAT_MASK; |
7f552300 L |
509 | } |
510 | ||
511 | /*-----------------------------------------------------------------------*/ | |
512 | /* Get Disk Status */ | |
513 | /*-----------------------------------------------------------------------*/ | |
514 | ||
515 | DSTATUS disk_status ( | |
1222f338 | 516 | BYTE drv /* Physical drive nmuber (0) */ |
7f552300 L |
517 | ) |
518 | { | |
1222f338 L |
519 | if (drv >= MAX_DRV) |
520 | return STA_NOINIT; | |
11b53d3f | 521 | return socket[drv].stat & STAT_MASK; |
7f552300 L |
522 | } |
523 | ||
524 | /*-----------------------------------------------------------------------*/ | |
525 | /* Read Sector(s) */ | |
526 | /*-----------------------------------------------------------------------*/ | |
527 | ||
528 | DRESULT disk_read ( | |
1222f338 L |
529 | BYTE drv, /* Physical drive nmuber (0) */ |
530 | BYTE *buff, /* Pointer to the data buffer to store read data */ | |
531 | DWORD sector, /* Start sector number (LBA) */ | |
532 | UINT count /* Sector count (1..255) */ | |
7f552300 L |
533 | ) |
534 | { | |
535 | BYTE cmd; | |
536 | ||
1222f338 L |
537 | if (drv >= MAX_DRV || !count) |
538 | return RES_PARERR; | |
539 | if (socket[drv].stat & STA_NOINIT) | |
540 | return RES_NOTRDY; | |
7f552300 | 541 | |
1222f338 L |
542 | /* Convert to byte address if needed */ |
543 | if (!(socket[drv].CardType & CT_BLOCK)) | |
544 | sector *= 512; | |
7f552300 | 545 | |
1222f338 L |
546 | /* READ_MULTIPLE_BLOCK : READ_SINGLE_BLOCK */ |
547 | cmd = count > 1 ? CMD18 : CMD17; | |
548 | if (send_cmd(drv, cmd, sector) == 0) { | |
7f552300 L |
549 | do { |
550 | if (!rcvr_datablock(buff, 512)) | |
551 | break; | |
552 | buff += 512; | |
553 | } while (--count); | |
554 | if (cmd == CMD18) | |
1222f338 | 555 | send_cmd(drv, CMD12, 0); /* STOP_TRANSMISSION */ |
7f552300 | 556 | } |
1222f338 | 557 | deselect(drv); |
7f552300 L |
558 | |
559 | return count ? RES_ERROR : RES_OK; | |
560 | } | |
561 | ||
562 | /*-----------------------------------------------------------------------*/ | |
563 | /* Write Sector(s) */ | |
564 | /*-----------------------------------------------------------------------*/ | |
565 | ||
566 | #if _USE_WRITE | |
567 | DRESULT disk_write ( | |
1222f338 L |
568 | BYTE drv, /* Physical drive nmuber (0) */ |
569 | const BYTE *buff, /* Pointer to the data to be written */ | |
570 | DWORD sector, /* Start sector number (LBA) */ | |
571 | UINT count /* Sector count (1..255) */ | |
7f552300 L |
572 | ) |
573 | { | |
1222f338 L |
574 | if (drv >= MAX_DRV || !count) |
575 | return RES_PARERR; | |
576 | if (socket[drv].stat & STA_NOINIT) | |
577 | return RES_NOTRDY; | |
578 | if (socket[drv].stat & STA_PROTECT) | |
579 | return RES_WRPRT; | |
580 | ||
581 | /* Convert to byte address if needed */ | |
582 | if (!(socket[drv].CardType & CT_BLOCK)) | |
583 | sector *= 512; | |
1222f338 L |
584 | |
585 | if (count == 1) { | |
586 | /* Single block write */ | |
587 | if ((send_cmd(drv, CMD24, sector) == 0) /* WRITE_BLOCK */ | |
7f552300 L |
588 | && xmit_datablock(buff, 0xFE)) |
589 | count = 0; | |
1222f338 L |
590 | } else { |
591 | /* Multiple block write */ | |
592 | if (socket[drv].CardType & CT_SDC) | |
593 | send_cmd(drv, ACMD23, count); | |
594 | if (send_cmd(drv, CMD25, sector) == 0) { | |
595 | /* WRITE_MULTIPLE_BLOCK */ | |
7f552300 | 596 | do { |
1222f338 L |
597 | if (!xmit_datablock(buff, 0xFC)) |
598 | break; | |
7f552300 | 599 | buff += 512; |
1222f338 | 600 | } while (--count); |
7f552300 | 601 | if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ |
1222f338 | 602 | count = 1; |
7f552300 L |
603 | } |
604 | } | |
1222f338 | 605 | deselect(drv); |
7f552300 L |
606 | |
607 | return count ? RES_ERROR : RES_OK; | |
608 | } | |
609 | #endif /* _USE_WRITE */ | |
610 | ||
611 | /*-----------------------------------------------------------------------*/ | |
612 | /* Miscellaneous Functions */ | |
613 | /*-----------------------------------------------------------------------*/ | |
614 | ||
615 | #if _USE_IOCTL | |
616 | DRESULT disk_ioctl ( | |
617 | BYTE drv, /* Physical drive nmuber (0) */ | |
618 | BYTE cmd, /* Control code */ | |
619 | void *buff /* Buffer to send/receive control data */ | |
620 | ) | |
621 | { | |
622 | DRESULT res; | |
623 | BYTE n, csd[16], *ptr = buff; | |
624 | DWORD csize; | |
625 | ||
1222f338 | 626 | if (drv >= MAX_DRV) |
7f552300 L |
627 | return RES_PARERR; |
628 | ||
629 | res = RES_ERROR; | |
630 | ||
1222f338 L |
631 | if (socket[drv].stat & STA_NOINIT) |
632 | return RES_NOTRDY; | |
7f552300 | 633 | |
a870134a L |
634 | /* TODO: SPI clock? */ |
635 | ||
7f552300 L |
636 | switch (cmd) { |
637 | case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ | |
1222f338 | 638 | if (select(drv)) |
7f552300 L |
639 | res = RES_OK; |
640 | break; | |
641 | ||
642 | case GET_SECTOR_COUNT: /* Get number of sectors on the disk (DWORD) */ | |
1222f338 | 643 | if ((send_cmd(drv, CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { |
7f552300 L |
644 | if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ |
645 | csize = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1; | |
646 | *(DWORD*)buff = csize << 10; | |
647 | } else { /* SDC ver 1.XX or MMC*/ | |
648 | n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; | |
649 | csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; | |
650 | *(DWORD*)buff = csize << (n - 9); | |
651 | } | |
652 | res = RES_OK; | |
653 | } | |
654 | break; | |
655 | ||
656 | case GET_BLOCK_SIZE: /* Get erase block size in unit of sector (DWORD) */ | |
f82d019d | 657 | if (socket[drv].CardType & CT_SD2) { /* SDv2? */ |
1222f338 | 658 | if (send_cmd(drv, ACMD13, 0) == 0) { /* Read SD status */ |
7f552300 L |
659 | spi_rcvr(); |
660 | if (rcvr_datablock(csd, 16)) { /* Read partial block */ | |
661 | for (n = 64 - 16; n; n--) | |
662 | spi_rcvr(); /* Purge trailing data */ | |
663 | *(DWORD*) buff = 16UL << (csd[10] >> 4); | |
664 | res = RES_OK; | |
665 | } | |
666 | } | |
667 | } else { /* SDv1 or MMCv3 */ | |
1222f338 | 668 | if ((send_cmd(drv, CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ |
f82d019d | 669 | if (socket[drv].CardType & CT_SD1) { /* SDv1 */ |
7f552300 L |
670 | *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); |
671 | } else { /* MMCv3 */ | |
672 | *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); | |
673 | } | |
674 | res = RES_OK; | |
675 | } | |
676 | } | |
677 | break; | |
678 | ||
679 | /* Following commands are never used by FatFs module */ | |
680 | ||
681 | case MMC_GET_TYPE: /* Get card type flags (1 byte) */ | |
f82d019d | 682 | *ptr = socket[drv].CardType; |
7f552300 L |
683 | res = RES_OK; |
684 | break; | |
685 | ||
686 | case MMC_GET_CSD: /* Receive CSD as a data block (16 bytes) */ | |
1222f338 | 687 | if (send_cmd(drv, CMD9, 0) == 0 /* READ_CSD */ |
7f552300 L |
688 | && rcvr_datablock(ptr, 16)) |
689 | res = RES_OK; | |
690 | break; | |
691 | ||
692 | case MMC_GET_CID: /* Receive CID as a data block (16 bytes) */ | |
1222f338 | 693 | if (send_cmd(drv, CMD10, 0) == 0 /* READ_CID */ |
7f552300 L |
694 | && rcvr_datablock(ptr, 16)) |
695 | res = RES_OK; | |
696 | break; | |
697 | ||
698 | case MMC_GET_OCR: /* Receive OCR as an R3 resp (4 bytes) */ | |
1222f338 | 699 | if (send_cmd(drv, CMD58, 0) == 0) { /* READ_OCR */ |
7f552300 L |
700 | for (n = 4; n; n--) |
701 | *ptr++ = spi_rcvr(); | |
702 | res = RES_OK; | |
703 | } | |
704 | break; | |
705 | ||
706 | case MMC_GET_SDSTAT: /* Receive SD status as a data block (64 bytes) */ | |
1222f338 | 707 | if (send_cmd(drv, ACMD13, 0) == 0) { /* SD_STATUS */ |
7f552300 L |
708 | spi_rcvr(); |
709 | if (rcvr_datablock(ptr, 64)) | |
710 | res = RES_OK; | |
711 | } | |
712 | break; | |
713 | ||
714 | case CTRL_POWER_OFF : /* Power off */ | |
1222f338 | 715 | power_off(drv); |
f82d019d | 716 | socket[drv].stat |= STA_NOINIT; |
7f552300 L |
717 | res = RES_OK; |
718 | break; | |
719 | ||
720 | default: | |
721 | res = RES_PARERR; | |
722 | } | |
723 | ||
1222f338 | 724 | deselect(drv); |
7f552300 L |
725 | |
726 | return res; | |
727 | } | |
728 | #endif /* _USE_IOCTL */ | |
729 | ||
730 | /*-----------------------------------------------------------------------*/ | |
731 | /* Device Timer Interrupt Procedure (Platform dependent) */ | |
732 | /*-----------------------------------------------------------------------*/ | |
733 | /* This function must be called in period of 10ms */ | |
734 | ||
735 | void disk_timerproc (void) | |
736 | { | |
737 | BYTE s; | |
738 | ||
f82d019d | 739 | s = socket[0].stat; |
1222f338 L |
740 | #ifdef SD_WP_0 |
741 | if (SD_WP_0_IN == 0) /* Write protected */ | |
742 | s |= STA_PROTECT; | |
15e476bc | 743 | else /* Write enabled */ |
1222f338 L |
744 | s &= ~STA_PROTECT; |
745 | #endif | |
15e476bc L |
746 | |
747 | #if defined SD_CD_0 | |
1222f338 L |
748 | if (SD_CD_0_IN == 0) /* Card inserted */ |
749 | s &= ~STA_NODISK; | |
15e476bc | 750 | else /* Socket empty */ |
1222f338 | 751 | s |= (STA_NODISK | STA_NOINIT); |
15e476bc L |
752 | #elif defined SD_CS_0_IN |
753 | if (SD_CS_0_DDR == 0) { | |
754 | if (SD_CS_0_IN == 1) /* Card inserted */ | |
755 | s &= ~STA_NODISK; | |
756 | else /* Socket empty */ | |
757 | s |= (STA_NODISK | STA_NOINIT); | |
758 | } | |
1222f338 | 759 | #endif |
15e476bc | 760 | socket[0].stat = s; /* Update MMC status */ |
7f552300 | 761 | |
1222f338 | 762 | s = socket[1].stat; |
f82d019d L |
763 | #ifdef SD_WP_1 |
764 | if (SD_WP_1_IN == 0) /* Write protected */ | |
7f552300 | 765 | s |= STA_PROTECT; |
15e476bc | 766 | else /* Write enabled */ |
7f552300 L |
767 | s &= ~STA_PROTECT; |
768 | #endif | |
15e476bc L |
769 | |
770 | #if defined SD_CD_1 | |
f82d019d | 771 | if (SD_CD_1_IN == 0) /* Card inserted */ |
7f552300 | 772 | s &= ~STA_NODISK; |
15e476bc | 773 | else /* Socket empty */ |
7f552300 | 774 | s |= (STA_NODISK | STA_NOINIT); |
15e476bc | 775 | #elif defined SD_CS_1_IN |
a870134a | 776 | if (SD_CS_1_DDR == 0) { |
15e476bc | 777 | if (SD_CS_1_IN == 1) /* Card inserted */ |
a870134a | 778 | s &= ~STA_NODISK; |
15e476bc | 779 | else /* Socket empty */ |
a870134a L |
780 | s |= (STA_NODISK | STA_NOINIT); |
781 | } | |
7f552300 | 782 | #endif |
1222f338 | 783 | socket[1].stat = s; /* Update MMC status */ |
7f552300 | 784 | } |