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Commit | Line | Data |
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7f552300 L |
1 | /*-----------------------------------------------------------------------*/ |
2 | /* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2007 */ | |
3 | /*-----------------------------------------------------------------------*/ | |
4 | /* Only spi_rcvr(), spi_xmit(), disk_timerproc() and some macros */ | |
5 | /* are platform dependent. */ | |
6 | /*-----------------------------------------------------------------------*/ | |
7 | ||
f82d019d | 8 | #include "common.h" |
7f552300 L |
9 | #include <stdbool.h> |
10 | #include "timer.h" | |
11 | #include "spi.h" | |
12 | #include "diskio.h" | |
a870134a | 13 | #include "debug.h" |
7f552300 | 14 | |
1222f338 | 15 | #define MAX_DRV 2 |
7f552300 | 16 | |
f82d019d L |
17 | /* Port Controls (Platform dependent) */ |
18 | /* SD card socket connections */ | |
19 | ||
15e476bc L |
20 | /* TODO: config.h cofig macros */ |
21 | ||
22 | //#define SD_CD_0 SBIT(PORT,) /* Card detect switch */ | |
1222f338 L |
23 | //#define SD_CD_0_IN SBIT(PIN,) |
24 | //#define SD_CD_0_DDR SBIT(DDR,) | |
25 | ||
15e476bc | 26 | //#define SD_WP_0 SBIT(PORT,) /* Write protect switch */ |
1222f338 L |
27 | //#define SD_WP_0_IN SBIT(PIN,) |
28 | //#define SD_WP_0_DDR SBIT(DDR,) | |
29 | ||
15e476bc | 30 | #define SD_CS_0 SBIT(PORTB,0) /* Chip select pin */ |
1222f338 L |
31 | #define SD_CS_0_IN SBIT(PINB,0) |
32 | #define SD_CS_0_DDR SBIT(DDRB,0) | |
33 | ||
15e476bc L |
34 | |
35 | //#define SD_CD_1 SBIT(PORTG,3) /* Card detect switch */ | |
8b6edd92 L |
36 | //#define SD_CD_1_IN SBIT(PING,3) |
37 | //#define SD_CD_1_DDR SBIT(DDRG,3) | |
f82d019d | 38 | |
15e476bc L |
39 | //#define SD_WP_1 SBIT(PORTG,5) /* Write protect switch */ |
40 | //#define SD_WP_1_IN SBIT(PING,5) | |
41 | //#define SD_WP_1_DDR SBIT(DDRG,5) | |
f82d019d L |
42 | |
43 | #define SD_CS_1 SBIT(PORTG,4) /* Chip select pin */ | |
44 | #define SD_CS_1_IN SBIT(PING,4) | |
45 | #define SD_CS_1_DDR SBIT(DDRG,4) | |
46 | ||
47 | ||
a870134a | 48 | #define SPI_CLK_SLOW() SPISetMMCInitClock() /* Set slow clock (100k-400k) */ |
15e476bc | 49 | #define SPI_CLK_FAST() SPISetFastClock() /* Set fast clock (depends on the CSD) */ |
f82d019d L |
50 | |
51 | /*-------------------------------------------------------------------------- | |
52 | Definitions for MMC/SDC command | |
53 | ---------------------------------------------------------------------------*/ | |
54 | ||
7f552300 L |
55 | #define CMD0 (0) /* GO_IDLE_STATE */ |
56 | #define CMD1 (1) /* SEND_OP_COND (MMC) */ | |
57 | #define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */ | |
58 | #define CMD8 (8) /* SEND_IF_COND */ | |
59 | #define CMD9 (9) /* SEND_CSD */ | |
60 | #define CMD10 (10) /* SEND_CID */ | |
61 | #define CMD12 (12) /* STOP_TRANSMISSION */ | |
62 | #define ACMD13 (0x80+13) /* SD_STATUS (SDC) */ | |
63 | #define CMD16 (16) /* SET_BLOCKLEN */ | |
64 | #define CMD17 (17) /* READ_SINGLE_BLOCK */ | |
65 | #define CMD18 (18) /* READ_MULTIPLE_BLOCK */ | |
66 | #define CMD23 (23) /* SET_BLOCK_COUNT (MMC) */ | |
67 | #define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ | |
68 | #define CMD24 (24) /* WRITE_BLOCK */ | |
69 | #define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ | |
70 | #define CMD55 (55) /* APP_CMD */ | |
71 | #define CMD58 (58) /* READ_OCR */ | |
72 | ||
73 | ||
7f552300 L |
74 | /*-------------------------------------------------------------------------- |
75 | ||
76 | Module Private Functions | |
77 | ||
78 | ---------------------------------------------------------------------------*/ | |
79 | ||
f82d019d L |
80 | struct sdsock_stat_s { |
81 | volatile DSTATUS stat; /* Disk/socket status */ | |
82 | BYTE CardType; /* Card type flags */ | |
83 | }; | |
7f552300 L |
84 | |
85 | static | |
f82d019d | 86 | struct sdsock_stat_s |
1222f338 | 87 | socket[MAX_DRV] = { |
f82d019d L |
88 | {.stat=STA_NOINIT}, |
89 | {.stat=STA_NOINIT} | |
90 | }; | |
7f552300 L |
91 | |
92 | /*-----------------------------------------------------------------------*/ | |
93 | /* Wait for card ready */ | |
94 | /*-----------------------------------------------------------------------*/ | |
95 | ||
96 | static | |
97 | int wait_ready (void) /* 1:OK, 0:Timeout */ | |
98 | { | |
99 | uint32_t to = get_timer(0); | |
100 | ||
101 | /* Wait for ready in timeout of 500ms */ | |
102 | do { | |
103 | if (spi_rcvr() == 0xFF) { | |
104 | return 1; | |
105 | } | |
106 | } while (get_timer(to) < 500); | |
107 | ||
108 | return 0; | |
109 | } | |
110 | ||
111 | /*-----------------------------------------------------------------------*/ | |
112 | /* Deselect the card and release SPI bus */ | |
113 | /*-----------------------------------------------------------------------*/ | |
114 | ||
115 | static | |
1222f338 | 116 | void deselect(BYTE drv) |
7f552300 | 117 | { |
8b6edd92 | 118 | //debug("*** enter deselect()\n"); |
1222f338 L |
119 | if (drv == 0) |
120 | SD_CS_0 = 1; | |
a870134a | 121 | else { |
1222f338 | 122 | SD_CS_1 = 1; |
a870134a L |
123 | } |
124 | ||
7f552300 | 125 | /* Dummy clock (TODO: force DO hi-z for multiple slave SPI) */ |
a870134a L |
126 | if (socket[drv].stat & STA_FAST) |
127 | SPI_CLK_FAST(); | |
128 | else | |
129 | SPI_CLK_SLOW(); | |
7f552300 | 130 | spi_rcvr(); |
a870134a L |
131 | SPI_OFF(); |
132 | ||
133 | if (drv == 0) { | |
134 | #ifndef SD_CD_0 | |
135 | // SD_CS_0 = 1; | |
136 | #endif | |
137 | } else { | |
138 | #ifndef SD_CD_1 | |
139 | SD_CS_1_DDR = 0; | |
140 | SD_CS_1 = 0; | |
141 | #endif | |
142 | } | |
8b6edd92 | 143 | //debug("*** exit deselect()\n"); |
7f552300 L |
144 | } |
145 | ||
7f552300 L |
146 | /*-----------------------------------------------------------------------*/ |
147 | /* Select the card and wait for ready */ | |
148 | /*-----------------------------------------------------------------------*/ | |
149 | ||
150 | static | |
1222f338 | 151 | int select(BYTE drv) /* 1:Successful, 0:Timeout */ |
7f552300 | 152 | { |
8b6edd92 | 153 | //debug("*** enter select()\n"); |
1222f338 L |
154 | if (drv == 0) |
155 | SD_CS_0 = 0; | |
a870134a L |
156 | else { |
157 | #ifndef SD_CD_1 | |
158 | SD_CS_1 = 1; | |
159 | SD_CS_1_DDR = 1; | |
160 | #endif | |
1222f338 | 161 | SD_CS_1 = 0; |
a870134a L |
162 | } |
163 | ||
164 | if (socket[drv].stat & STA_FAST) | |
165 | SPI_CLK_FAST(); | |
166 | else | |
167 | SPI_CLK_SLOW(); | |
168 | ||
7f552300 L |
169 | /* Dummy clock (force DO enabled) */ |
170 | spi_rcvr(); | |
171 | ||
172 | if (wait_ready()) { | |
8b6edd92 | 173 | //debug("*** exit select() == 1\n"); |
7f552300 L |
174 | return 1; /* OK */ |
175 | } | |
1222f338 | 176 | deselect(drv); |
8b6edd92 | 177 | //debug("*** exit select() == 0\n"); |
7f552300 L |
178 | |
179 | return 0; /* Timeout */ | |
180 | } | |
181 | ||
182 | /*-----------------------------------------------------------------------*/ | |
183 | /* Power Control (Platform dependent) */ | |
184 | /*-----------------------------------------------------------------------*/ | |
185 | /* When the target system does not support socket power control, there */ | |
186 | /* is nothing to do in these functions and chk_power always returns 1. */ | |
187 | ||
188 | static | |
1222f338 | 189 | void power_on(BYTE drv) |
7f552300 | 190 | { |
8b6edd92 | 191 | //debug("*** enter power_on()\n"); |
7f552300 | 192 | |
1222f338 L |
193 | if (drv == 0) { |
194 | #ifdef SD_PWR_0 | |
1222f338 | 195 | SD_PWR_0 = 0; /* Drives PWR pin high */ |
1222f338 L |
196 | #endif |
197 | ||
1222f338 | 198 | } else { |
f82d019d | 199 | #ifdef SD_PWR_1 |
1222f338 | 200 | SD_PWR_1 = 0; /* Drives PWR pin high */ |
15e476bc L |
201 | #endif |
202 | } | |
203 | #if defined SD_PWR_0 || defined SD_PWR_1 | |
1222f338 L |
204 | for (uint32_t to = get_timer(0); get_timer(to) < 30;) |
205 | ; /* Wait for 30ms */ | |
7f552300 | 206 | #endif |
8b6edd92 | 207 | //debug("*** exit power_on()\n"); |
7f552300 L |
208 | } |
209 | ||
210 | static | |
1222f338 | 211 | void power_off(BYTE drv) |
7f552300 | 212 | { |
8b6edd92 | 213 | //debug("*** enter power_off()\n"); |
1222f338 L |
214 | select(drv); /* Wait for card ready */ |
215 | deselect(drv); | |
7f552300 | 216 | |
1222f338 L |
217 | if (drv == 0) { |
218 | #ifdef SD_PWR_0 | |
219 | SD_PWR_0 = 1; /* Socket power OFF */ | |
220 | #endif | |
221 | } else { | |
f82d019d | 222 | #ifdef SD_PWR_1 |
1222f338 | 223 | SD_PWR_1 = 1; /* Socket power OFF */ |
7f552300 | 224 | #endif |
1222f338 L |
225 | } |
226 | socket[drv].stat |= STA_NOINIT; | |
8b6edd92 | 227 | //debug("*** exit power_off()\n"); |
7f552300 L |
228 | } |
229 | ||
230 | #if 0 | |
231 | static | |
1222f338 | 232 | int chk_power(BYTE drv) /* Socket power state: 0=off, 1=on */ |
7f552300 | 233 | { |
1222f338 L |
234 | if (drv == 0) { |
235 | #ifdef SD_PWR_0 | |
236 | return SD_PWR_0 == 0; | |
237 | #else | |
238 | return 1; | |
239 | #endif /* SD_PWR_PIN */ | |
240 | } else { | |
f82d019d | 241 | #ifdef SD_PWR_1 |
1222f338 | 242 | return SD_PWR_1 == 0; |
7f552300 | 243 | #else |
1222f338 | 244 | return 1; |
7f552300 | 245 | #endif /* SD_PWR_PIN */ |
1222f338 | 246 | } |
7f552300 L |
247 | } |
248 | #endif | |
249 | ||
250 | /*-----------------------------------------------------------------------*/ | |
251 | /* Receive a data packet from MMC */ | |
252 | /*-----------------------------------------------------------------------*/ | |
253 | ||
254 | static | |
255 | int rcvr_datablock ( | |
256 | BYTE *buff, /* Data buffer to store received data */ | |
257 | UINT btr /* Byte count (must be multiple of 4) */ | |
258 | ) { | |
259 | BYTE token, tmp; | |
260 | uint32_t to = get_timer(0); | |
261 | ||
262 | /* Wait for data packet in timeout of 200ms */ | |
263 | do { | |
264 | token = spi_rcvr(); | |
265 | } while ((token == 0xFF) && get_timer(to) < 200); | |
266 | if(token != 0xFE) return 0; /* If not valid data token, retutn with error */ | |
267 | ||
268 | tmp = spi_rcvr(); /* shift in first byte */ | |
269 | spi_write(0xff); /* start shift in next byte */ | |
270 | while (--btr) { | |
271 | *buff++ = tmp; | |
272 | asm volatile (""::"r"(buff), "r"(btr)); | |
273 | spi_wait(); | |
274 | tmp = SPDR; | |
275 | spi_write(0xff); | |
276 | } | |
277 | *buff = tmp; /* store last byte in buffer while SPI module shifts in crc part1 */ | |
278 | spi_wait(); | |
279 | spi_rcvr(); /* second crc */ | |
280 | ||
281 | return 1; /* Return with success */ | |
282 | } | |
283 | ||
284 | /*-----------------------------------------------------------------------*/ | |
285 | /* Send a data packet to MMC */ | |
286 | /*-----------------------------------------------------------------------*/ | |
287 | ||
288 | #if _USE_WRITE | |
289 | static | |
290 | int xmit_datablock ( | |
291 | const BYTE *buff, /* 512 byte data block to be transmitted */ | |
292 | BYTE token /* Data/Stop token */ | |
293 | ) | |
294 | { | |
295 | BYTE resp, tmp; | |
296 | UINT btr; | |
297 | ||
298 | if (!wait_ready()) return 0; | |
299 | ||
300 | spi_write(token); /* Xmit data token */ | |
301 | if (token != 0xFD) { /* Is data token */ | |
302 | btr = 512; | |
303 | do { | |
304 | tmp = *buff++; | |
305 | spi_wait(); | |
306 | spi_write(tmp); | |
307 | }while (--btr); | |
308 | spi_wait(); | |
309 | spi_xmit(0xff); /* CRC (Dummy) */ | |
310 | spi_xmit(0xff); | |
311 | resp = spi_rcvr(); /* Reveive data response */ | |
312 | return ((resp & 0x1F) != 0x05) ? 0 : 1; /* If not accepted, return with error */ | |
313 | } | |
314 | ||
315 | spi_wait(); | |
316 | return 1; | |
317 | } | |
318 | #endif /* _USE_WRITE */ | |
319 | ||
320 | /*-----------------------------------------------------------------------*/ | |
321 | /* Send a command packet to MMC */ | |
322 | /*-----------------------------------------------------------------------*/ | |
323 | ||
324 | static | |
325 | BYTE send_cmd ( /* Returns R1 resp (bit7==1:Send failed) */ | |
1222f338 L |
326 | BYTE drv, /* Physical drive nmuber (0) */ |
327 | BYTE cmd, /* Command index */ | |
328 | DWORD arg /* Argument */ | |
7f552300 L |
329 | ) { |
330 | union { | |
331 | DWORD as32; | |
332 | BYTE as8[4]; | |
333 | } argtmp; | |
334 | BYTE n, res; | |
335 | ||
8b6edd92 | 336 | //debug("*** send_cmd( %.2x )\n", cmd); |
7f552300 L |
337 | |
338 | if (cmd & 0x80) { /* ACMD<n> is the command sequense of CMD55-CMD<n> */ | |
339 | cmd &= 0x7F; | |
1222f338 | 340 | res = send_cmd(drv, CMD55, 0); |
7f552300 L |
341 | if (res > 1) |
342 | return res; | |
343 | } | |
344 | ||
345 | /* Select the card and wait for ready except to stop multiple block read */ | |
346 | if (cmd != CMD12) { | |
1222f338 L |
347 | deselect(drv); |
348 | if (!select(drv)) | |
7f552300 L |
349 | return 0xFF; |
350 | } | |
351 | ||
352 | /* Send command packet */ | |
353 | spi_xmit(0x40 | cmd); /* Start + Command index */ | |
354 | argtmp.as32 = arg; | |
355 | spi_xmit(argtmp.as8[3]); /* Argument[31..24] */ | |
356 | spi_xmit(argtmp.as8[2]); /* Argument[23..16] */ | |
357 | spi_xmit(argtmp.as8[1]); /* Argument[15..8] */ | |
358 | spi_xmit(argtmp.as8[0]); /* Argument[7..0] */ | |
359 | ||
360 | n = 0x01; /* Dummy CRC + Stop */ | |
361 | if (cmd == CMD0) | |
362 | n = 0x95; /* Valid CRC for CMD0(0) */ | |
363 | if (cmd == CMD8) | |
364 | n = 0x87; /* Valid CRC for CMD8(0x1AA) */ | |
365 | spi_xmit(n); | |
366 | ||
367 | /* Receive command response */ | |
368 | if (cmd == CMD12) | |
369 | spi_rcvr(); /* Skip a stuff byte when stop reading */ | |
370 | n = 10; /* Wait for a valid response in timeout of 10 attempts */ | |
371 | do | |
372 | res = spi_rcvr(); | |
373 | while ((res & 0x80) && --n); | |
374 | ||
375 | return res; /* Return with the response value */ | |
376 | } | |
377 | ||
378 | /*-------------------------------------------------------------------------- | |
379 | ||
380 | Public Functions | |
381 | ||
382 | ---------------------------------------------------------------------------*/ | |
383 | ||
15e476bc L |
384 | void setup_mmc(void) |
385 | { | |
386 | #ifdef SD_PWR_0 | |
387 | SD_PWR_1 = 1; /* Drives PWR pin low */ | |
388 | SD_PWR_0_DDR = 1; /* Turns on PWR pin as output */ | |
389 | #endif | |
390 | #ifdef SD_WP_0 | |
391 | SD_WP_0_DDR = 0; | |
392 | SD_WP_0 = 1; /* Pullup */ | |
393 | #endif | |
394 | ||
395 | #ifdef SD_PWR_1 | |
396 | SD_PWR_1 = 1; /* Drives PWR pin low */ | |
397 | SD_PWR_1_DDR = 1; /* Turns on PWR pin as output */ | |
398 | #endif | |
399 | #ifdef SD_WP_1 | |
400 | SD_WP_1_DDR = 0; | |
401 | SD_WP_1 = 1; /* Pullup */ | |
402 | #endif | |
403 | ||
404 | /* SPI as master */ | |
405 | PRR0 &= ~_BV(PRSPI); | |
406 | SPI_DDR = (SPI_DDR & ~(_BV(SPI_MISO) | _BV(SPI_SS))) | |
407 | | _BV(SPI_MOSI) | _BV(SPI_SCK); | |
408 | SPI_PORT = SPI_PORT & ~(_BV(SPI_MOSI) | _BV(SPI_SCK)); | |
409 | ||
410 | #if defined SD_CD_0 | |
411 | SD_CD_0_DDR = 0; | |
412 | SD_CD_0 = 1; | |
413 | #elif defined SD_CS_0_IN | |
414 | SD_CS_0_DDR = 0; | |
415 | SD_CS_0 = 0; | |
416 | #else | |
417 | SD_CS_0_DDR = 1; | |
418 | SD_CS_0 = 1; | |
419 | #endif | |
420 | ||
421 | #if defined SD_CD_1 | |
422 | SD_CD_1_DDR = 0; | |
423 | SD_CD_1 = 1; | |
424 | #elif defined SD_CS_1_IN | |
425 | SD_CS_1_DDR = 0; | |
426 | SD_CS_1 = 0; | |
427 | #else | |
428 | SD_CS_1_DDR = 1; | |
429 | SD_CS_1 = 1; | |
430 | #endif | |
431 | } | |
432 | ||
7f552300 L |
433 | /*-----------------------------------------------------------------------*/ |
434 | /* Initialize Disk Drive */ | |
435 | /*-----------------------------------------------------------------------*/ | |
436 | ||
437 | #define MMC_INIT_TO 1000 /* 1s */ | |
438 | ||
439 | DSTATUS disk_initialize ( | |
440 | BYTE drv /* Physical drive nmuber (0) */ | |
441 | ) | |
442 | { | |
443 | BYTE n, cmd, ty, ocr[4]; | |
444 | ||
1222f338 | 445 | if (drv >= MAX_DRV) |
7f552300 | 446 | return STA_NOINIT; /* Supports only single drive */ |
f82d019d L |
447 | if (socket[drv].stat & STA_NODISK) |
448 | return socket[drv].stat; /* No card in the socket */ | |
7f552300 | 449 | |
1222f338 | 450 | power_on(drv); /* Force socket power on */ |
a870134a L |
451 | socket[drv].stat &= ~STA_FAST; |
452 | SPI_CLK_SLOW(); | |
7f552300 L |
453 | for (n = 10; n; n--) |
454 | spi_rcvr(); /* 80 dummy clocks */ | |
455 | ||
456 | ty = 0; | |
1222f338 | 457 | if (send_cmd(drv, CMD0, 0) == 1) { /* Enter Idle state */ |
7f552300 L |
458 | /* Init timeout timer */ |
459 | uint32_t timer = get_timer(0); | |
460 | ||
1222f338 L |
461 | if (send_cmd(drv, CMD8, 0x1AA) == 1) { /* SDv2? */ |
462 | /* Get trailing return value of R7 resp */ | |
463 | for (n = 0; n < 4; n++) | |
464 | ocr[n] = spi_rcvr(); | |
465 | if (ocr[2] == 0x01 && ocr[3] == 0xAA) { | |
466 | /* The card can work at vdd range of 2.7-3.6V */ | |
467 | while (get_timer(timer) < MMC_INIT_TO | |
468 | && send_cmd(drv, ACMD41, 1UL << 30)) | |
469 | ; /* Wait for leaving idle state (ACMD41 with HCS bit) */ | |
470 | if (get_timer(timer) < MMC_INIT_TO && send_cmd(drv, CMD58, 0) == 0) { | |
471 | /* Check CCS bit in the OCR */ | |
472 | for (n = 0; n < 4; n++) | |
473 | ocr[n] = spi_rcvr(); | |
7f552300 L |
474 | ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* SDv2 */ |
475 | } | |
476 | } | |
477 | } else { /* SDv1 or MMCv3 */ | |
1222f338 | 478 | if (send_cmd(drv, ACMD41, 0) <= 1) { |
7f552300 L |
479 | ty = CT_SD1; cmd = ACMD41; /* SDv1 */ |
480 | } else { | |
481 | ty = CT_MMC; cmd = CMD1; /* MMCv3 */ | |
482 | } | |
483 | ||
484 | /* Wait for leaving idle state */ | |
1222f338 L |
485 | while (get_timer(timer) < MMC_INIT_TO && send_cmd(drv, cmd, 0)) |
486 | ; | |
7f552300 L |
487 | |
488 | /* Set R/W block length to 512 */ | |
1222f338 | 489 | if (!(get_timer(timer) < MMC_INIT_TO) || send_cmd(drv, CMD16, 512) != 0) |
7f552300 L |
490 | ty = 0; |
491 | } | |
492 | } | |
f82d019d | 493 | socket[drv].CardType = ty; |
1222f338 | 494 | deselect(drv); |
7f552300 L |
495 | |
496 | if (ty) { /* Initialization succeded */ | |
8b6edd92 L |
497 | /* Clear STA_NOINIT */ |
498 | socket[drv].stat = (socket[drv].stat & ~STA_NOINIT) | STA_FAST; | |
7f552300 | 499 | } else { /* Initialization failed */ |
1222f338 | 500 | power_off(drv); |
7f552300 L |
501 | } |
502 | ||
f82d019d | 503 | return socket[drv].stat; |
7f552300 L |
504 | } |
505 | ||
506 | /*-----------------------------------------------------------------------*/ | |
507 | /* Get Disk Status */ | |
508 | /*-----------------------------------------------------------------------*/ | |
509 | ||
510 | DSTATUS disk_status ( | |
1222f338 | 511 | BYTE drv /* Physical drive nmuber (0) */ |
7f552300 L |
512 | ) |
513 | { | |
1222f338 L |
514 | if (drv >= MAX_DRV) |
515 | return STA_NOINIT; | |
f82d019d | 516 | return socket[drv].stat; |
7f552300 L |
517 | } |
518 | ||
519 | /*-----------------------------------------------------------------------*/ | |
520 | /* Read Sector(s) */ | |
521 | /*-----------------------------------------------------------------------*/ | |
522 | ||
523 | DRESULT disk_read ( | |
1222f338 L |
524 | BYTE drv, /* Physical drive nmuber (0) */ |
525 | BYTE *buff, /* Pointer to the data buffer to store read data */ | |
526 | DWORD sector, /* Start sector number (LBA) */ | |
527 | UINT count /* Sector count (1..255) */ | |
7f552300 L |
528 | ) |
529 | { | |
530 | BYTE cmd; | |
531 | ||
1222f338 L |
532 | if (drv >= MAX_DRV || !count) |
533 | return RES_PARERR; | |
534 | if (socket[drv].stat & STA_NOINIT) | |
535 | return RES_NOTRDY; | |
7f552300 | 536 | |
1222f338 L |
537 | /* Convert to byte address if needed */ |
538 | if (!(socket[drv].CardType & CT_BLOCK)) | |
539 | sector *= 512; | |
7f552300 | 540 | |
1222f338 L |
541 | /* READ_MULTIPLE_BLOCK : READ_SINGLE_BLOCK */ |
542 | cmd = count > 1 ? CMD18 : CMD17; | |
543 | if (send_cmd(drv, cmd, sector) == 0) { | |
7f552300 L |
544 | do { |
545 | if (!rcvr_datablock(buff, 512)) | |
546 | break; | |
547 | buff += 512; | |
548 | } while (--count); | |
549 | if (cmd == CMD18) | |
1222f338 | 550 | send_cmd(drv, CMD12, 0); /* STOP_TRANSMISSION */ |
7f552300 | 551 | } |
1222f338 | 552 | deselect(drv); |
7f552300 L |
553 | |
554 | return count ? RES_ERROR : RES_OK; | |
555 | } | |
556 | ||
557 | /*-----------------------------------------------------------------------*/ | |
558 | /* Write Sector(s) */ | |
559 | /*-----------------------------------------------------------------------*/ | |
560 | ||
561 | #if _USE_WRITE | |
562 | DRESULT disk_write ( | |
1222f338 L |
563 | BYTE drv, /* Physical drive nmuber (0) */ |
564 | const BYTE *buff, /* Pointer to the data to be written */ | |
565 | DWORD sector, /* Start sector number (LBA) */ | |
566 | UINT count /* Sector count (1..255) */ | |
7f552300 L |
567 | ) |
568 | { | |
1222f338 L |
569 | if (drv >= MAX_DRV || !count) |
570 | return RES_PARERR; | |
571 | if (socket[drv].stat & STA_NOINIT) | |
572 | return RES_NOTRDY; | |
573 | if (socket[drv].stat & STA_PROTECT) | |
574 | return RES_WRPRT; | |
575 | ||
576 | /* Convert to byte address if needed */ | |
577 | if (!(socket[drv].CardType & CT_BLOCK)) | |
578 | sector *= 512; | |
1222f338 L |
579 | |
580 | if (count == 1) { | |
581 | /* Single block write */ | |
582 | if ((send_cmd(drv, CMD24, sector) == 0) /* WRITE_BLOCK */ | |
7f552300 L |
583 | && xmit_datablock(buff, 0xFE)) |
584 | count = 0; | |
1222f338 L |
585 | } else { |
586 | /* Multiple block write */ | |
587 | if (socket[drv].CardType & CT_SDC) | |
588 | send_cmd(drv, ACMD23, count); | |
589 | if (send_cmd(drv, CMD25, sector) == 0) { | |
590 | /* WRITE_MULTIPLE_BLOCK */ | |
7f552300 | 591 | do { |
1222f338 L |
592 | if (!xmit_datablock(buff, 0xFC)) |
593 | break; | |
7f552300 | 594 | buff += 512; |
1222f338 | 595 | } while (--count); |
7f552300 | 596 | if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ |
1222f338 | 597 | count = 1; |
7f552300 L |
598 | } |
599 | } | |
1222f338 | 600 | deselect(drv); |
7f552300 L |
601 | |
602 | return count ? RES_ERROR : RES_OK; | |
603 | } | |
604 | #endif /* _USE_WRITE */ | |
605 | ||
606 | /*-----------------------------------------------------------------------*/ | |
607 | /* Miscellaneous Functions */ | |
608 | /*-----------------------------------------------------------------------*/ | |
609 | ||
610 | #if _USE_IOCTL | |
611 | DRESULT disk_ioctl ( | |
612 | BYTE drv, /* Physical drive nmuber (0) */ | |
613 | BYTE cmd, /* Control code */ | |
614 | void *buff /* Buffer to send/receive control data */ | |
615 | ) | |
616 | { | |
617 | DRESULT res; | |
618 | BYTE n, csd[16], *ptr = buff; | |
619 | DWORD csize; | |
620 | ||
1222f338 | 621 | if (drv >= MAX_DRV) |
7f552300 L |
622 | return RES_PARERR; |
623 | ||
624 | res = RES_ERROR; | |
625 | ||
1222f338 L |
626 | if (socket[drv].stat & STA_NOINIT) |
627 | return RES_NOTRDY; | |
7f552300 | 628 | |
a870134a L |
629 | /* TODO: SPI clock? */ |
630 | ||
7f552300 L |
631 | switch (cmd) { |
632 | case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ | |
1222f338 | 633 | if (select(drv)) |
7f552300 L |
634 | res = RES_OK; |
635 | break; | |
636 | ||
637 | case GET_SECTOR_COUNT: /* Get number of sectors on the disk (DWORD) */ | |
1222f338 | 638 | if ((send_cmd(drv, CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { |
7f552300 L |
639 | if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */ |
640 | csize = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1; | |
641 | *(DWORD*)buff = csize << 10; | |
642 | } else { /* SDC ver 1.XX or MMC*/ | |
643 | n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; | |
644 | csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; | |
645 | *(DWORD*)buff = csize << (n - 9); | |
646 | } | |
647 | res = RES_OK; | |
648 | } | |
649 | break; | |
650 | ||
651 | case GET_BLOCK_SIZE: /* Get erase block size in unit of sector (DWORD) */ | |
f82d019d | 652 | if (socket[drv].CardType & CT_SD2) { /* SDv2? */ |
1222f338 | 653 | if (send_cmd(drv, ACMD13, 0) == 0) { /* Read SD status */ |
7f552300 L |
654 | spi_rcvr(); |
655 | if (rcvr_datablock(csd, 16)) { /* Read partial block */ | |
656 | for (n = 64 - 16; n; n--) | |
657 | spi_rcvr(); /* Purge trailing data */ | |
658 | *(DWORD*) buff = 16UL << (csd[10] >> 4); | |
659 | res = RES_OK; | |
660 | } | |
661 | } | |
662 | } else { /* SDv1 or MMCv3 */ | |
1222f338 | 663 | if ((send_cmd(drv, CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ |
f82d019d | 664 | if (socket[drv].CardType & CT_SD1) { /* SDv1 */ |
7f552300 L |
665 | *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); |
666 | } else { /* MMCv3 */ | |
667 | *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); | |
668 | } | |
669 | res = RES_OK; | |
670 | } | |
671 | } | |
672 | break; | |
673 | ||
674 | /* Following commands are never used by FatFs module */ | |
675 | ||
676 | case MMC_GET_TYPE: /* Get card type flags (1 byte) */ | |
f82d019d | 677 | *ptr = socket[drv].CardType; |
7f552300 L |
678 | res = RES_OK; |
679 | break; | |
680 | ||
681 | case MMC_GET_CSD: /* Receive CSD as a data block (16 bytes) */ | |
1222f338 | 682 | if (send_cmd(drv, CMD9, 0) == 0 /* READ_CSD */ |
7f552300 L |
683 | && rcvr_datablock(ptr, 16)) |
684 | res = RES_OK; | |
685 | break; | |
686 | ||
687 | case MMC_GET_CID: /* Receive CID as a data block (16 bytes) */ | |
1222f338 | 688 | if (send_cmd(drv, CMD10, 0) == 0 /* READ_CID */ |
7f552300 L |
689 | && rcvr_datablock(ptr, 16)) |
690 | res = RES_OK; | |
691 | break; | |
692 | ||
693 | case MMC_GET_OCR: /* Receive OCR as an R3 resp (4 bytes) */ | |
1222f338 | 694 | if (send_cmd(drv, CMD58, 0) == 0) { /* READ_OCR */ |
7f552300 L |
695 | for (n = 4; n; n--) |
696 | *ptr++ = spi_rcvr(); | |
697 | res = RES_OK; | |
698 | } | |
699 | break; | |
700 | ||
701 | case MMC_GET_SDSTAT: /* Receive SD status as a data block (64 bytes) */ | |
1222f338 | 702 | if (send_cmd(drv, ACMD13, 0) == 0) { /* SD_STATUS */ |
7f552300 L |
703 | spi_rcvr(); |
704 | if (rcvr_datablock(ptr, 64)) | |
705 | res = RES_OK; | |
706 | } | |
707 | break; | |
708 | ||
709 | case CTRL_POWER_OFF : /* Power off */ | |
1222f338 | 710 | power_off(drv); |
f82d019d | 711 | socket[drv].stat |= STA_NOINIT; |
7f552300 L |
712 | res = RES_OK; |
713 | break; | |
714 | ||
715 | default: | |
716 | res = RES_PARERR; | |
717 | } | |
718 | ||
1222f338 | 719 | deselect(drv); |
7f552300 L |
720 | |
721 | return res; | |
722 | } | |
723 | #endif /* _USE_IOCTL */ | |
724 | ||
725 | /*-----------------------------------------------------------------------*/ | |
726 | /* Device Timer Interrupt Procedure (Platform dependent) */ | |
727 | /*-----------------------------------------------------------------------*/ | |
728 | /* This function must be called in period of 10ms */ | |
729 | ||
730 | void disk_timerproc (void) | |
731 | { | |
732 | BYTE s; | |
733 | ||
f82d019d | 734 | s = socket[0].stat; |
1222f338 L |
735 | #ifdef SD_WP_0 |
736 | if (SD_WP_0_IN == 0) /* Write protected */ | |
737 | s |= STA_PROTECT; | |
15e476bc | 738 | else /* Write enabled */ |
1222f338 L |
739 | s &= ~STA_PROTECT; |
740 | #endif | |
15e476bc L |
741 | |
742 | #if defined SD_CD_0 | |
1222f338 L |
743 | if (SD_CD_0_IN == 0) /* Card inserted */ |
744 | s &= ~STA_NODISK; | |
15e476bc | 745 | else /* Socket empty */ |
1222f338 | 746 | s |= (STA_NODISK | STA_NOINIT); |
15e476bc L |
747 | #elif defined SD_CS_0_IN |
748 | if (SD_CS_0_DDR == 0) { | |
749 | if (SD_CS_0_IN == 1) /* Card inserted */ | |
750 | s &= ~STA_NODISK; | |
751 | else /* Socket empty */ | |
752 | s |= (STA_NODISK | STA_NOINIT); | |
753 | } | |
1222f338 | 754 | #endif |
15e476bc | 755 | socket[0].stat = s; /* Update MMC status */ |
7f552300 | 756 | |
1222f338 | 757 | s = socket[1].stat; |
f82d019d L |
758 | #ifdef SD_WP_1 |
759 | if (SD_WP_1_IN == 0) /* Write protected */ | |
7f552300 | 760 | s |= STA_PROTECT; |
15e476bc | 761 | else /* Write enabled */ |
7f552300 L |
762 | s &= ~STA_PROTECT; |
763 | #endif | |
15e476bc L |
764 | |
765 | #if defined SD_CD_1 | |
f82d019d | 766 | if (SD_CD_1_IN == 0) /* Card inserted */ |
7f552300 | 767 | s &= ~STA_NODISK; |
15e476bc | 768 | else /* Socket empty */ |
7f552300 | 769 | s |= (STA_NODISK | STA_NOINIT); |
15e476bc | 770 | #elif defined SD_CS_1_IN |
a870134a | 771 | if (SD_CS_1_DDR == 0) { |
15e476bc | 772 | if (SD_CS_1_IN == 1) /* Card inserted */ |
a870134a | 773 | s &= ~STA_NODISK; |
15e476bc | 774 | else /* Socket empty */ |
a870134a L |
775 | s |= (STA_NODISK | STA_NOINIT); |
776 | } | |
7f552300 | 777 | #endif |
1222f338 | 778 | socket[1].stat = s; /* Update MMC status */ |
7f552300 | 779 | } |