projects / z180-stamp.git / blame
| Commit | Line | Data |
|---|---|---|
| a16ba2b0 L |
1 | .xlist\r |
| 2 | \r | |
| 3 | ;;\r | |
| 4 | ;; HD64180/Z180 Register Definitions\r | |
| 5 | ;;\r | |
| 6 | \r | |
| 7 | \r | |
| 8 | b2m macro name,nr\r | |
| 9 | name equ nr\r | |
| 10 | M_&name equ 1 shl nr\r | |
| 11 | endm\r | |
| 12 | \r | |
| 13 | ; ifndef IOBASE\r | |
| 14 | IOBASE equ 0\r | |
| 15 | ; endif\r | |
| 16 | \r | |
| 17 | cntla0 equ IOBASE+00h ;ASCI Control Register A Channel 0\r | |
| 18 | cntla1 equ IOBASE+01h ;ASCI Control Register A Channel 1\r | |
| 19 | b2m MPE, 7 ;Multi-Processor Mode Enable\r | |
| 20 | b2m RE, 6 ;Receiver Enable\r | |
| 21 | b2m TE, 5 ;Transmitter Enable\r | |
| 22 | b2m RTS0, 4 ;Request to Send Channel 0\r | |
| 23 | b2m CKA1D, 4 ;\r | |
| 24 | b2m MPBR, 3 ;Multiprocessor Bit Receive (Read)\r | |
| 25 | b2m EFR, 3 ;Error Flag Reset (Write)\r | |
| 26 | b2m MOD2, 2 ;Data Format Mode 1 = 8-Bit data\r | |
| 27 | b2m NOD1, 1 ;1 = Parity enabled\r | |
| 28 | b2m MOD0, 0 ;1 = 2 stop bits\r | |
| 29 | \r | |
| 30 | cntlb0 equ IOBASE+02h ;ASCI Control Register B Channel 0\r | |
| 31 | cntlb1 equ IOBASE+03h ;ASCI Control Register B Channel 1\r | |
| 32 | b2m MPBT,7 ;Multiprocessor Bit Transmit\r | |
| 33 | b2m MP,6 ;Multiprocessor Mode\r | |
| 34 | b2m CTS,5 ;Clear to Send\r | |
| 35 | b2m PS,5 ;Prescale\r | |
| 36 | b2m PEO,4 ;Parity Even Odd\r | |
| 37 | b2m DR,3 ;Divede Ratio\r | |
| 38 | b2m SS2,2 ;Source/Speed Select 2,1,0\r | |
| 39 | b2m SS1,1 ;\r | |
| 40 | b2m SS0,0 ;\r | |
| 41 | \r | |
| 42 | stat0 equ IOBASE+04h ;ASCI Status Channel 0\r | |
| 43 | stat1 equ IOBASE+05h ;ASCI Status Channel 1\r | |
| 44 | b2m RDRF,7 ;Receive Data Register Full\r | |
| 45 | b2m OVRN,6 ;Overrun Error\r | |
| 46 | b2m PERR,5 ;Parity Error (M80: PE conflicts with JP/CALL cc)\r | |
| 47 | b2m FE,4 ;Framing Error\r | |
| 48 | b2m RIE,3 ;Receive Interrupt Enable\r | |
| 49 | b2m DCD0,2 ;Data Carrier Detect (Ch 0)\r | |
| 50 | b2m CTS1E,2 ;Clear To Send (Ch 1)\r | |
| 51 | b2m TDRE,1 ;Transmit Data Register Empty\r | |
| 52 | b2m TIE,0 ;Transmit Interrupt Enable\r | |
| 53 | \r | |
| 815c1735 L |
54 | tdr0 equ IOBASE+06h ;ASCI Transmit Data\r |
| 55 | tdr1 equ IOBASE+07h ;ASCI Transmit Data\r | |
| 56 | rdr0 equ IOBASE+08h ;ASCI Receive Data\r | |
| 57 | rdr1 equ IOBASE+09h ;ASCI Receive Data\r | |
| a16ba2b0 L |
58 | \r |
| 59 | cntr equ IOBASE+0Ah ;CSI/O Control Register\r | |
| 60 | trdr equ IOBASE+0Bh ;CSI/O Transmit/Receive Data Register\r | |
| 61 | \r | |
| 62 | tmdr0l equ IOBASE+0Ch ;Timer Data Register Channel 0\r | |
| 63 | tmdr0h equ IOBASE+0Dh ;\r | |
| 64 | rldr0l equ IOBASE+0Eh ;Timer Reload Register Channel 0\r | |
| 65 | rldr0h equ IOBASE+0Fh ;\r | |
| 66 | tcr equ IOBASE+10h ;Timer Control Register\r | |
| 67 | b2m TIF1,7 ;Timer Interrupt Flag\r | |
| 68 | b2m TIF0,6 ;\r | |
| 69 | b2m TIE1,5 ;Timer Interrupt Enable\r | |
| 70 | b2m TIE0,4 ;\r | |
| 71 | b2m TOC1,3 ;Timer Output Control\r | |
| 72 | b2m TOC0,2 ;\r | |
| 73 | b2m TDE1,1 ;Timer Down Count Enable\r | |
| 74 | b2m TDE0,0 ;\r | |
| 75 | \r | |
| 76 | \r | |
| 77 | asext0 equ IOBASE+12h ;ASCI Extension Control Register\r | |
| 78 | asext1 equ IOBASE+13h ;ASCI Extension Control Register\r | |
| 79 | \r | |
| 80 | tmdr1l equ IOBASE+14h ;Timer Data Register Channel 1\r | |
| 81 | tmdr1h equ IOBASE+15h ;\r | |
| 82 | rldr1l equ IOBASE+16h ;Timer Reload Register Channel 1\r | |
| 83 | rldr1h equ IOBASE+17h ;\r | |
| 84 | \r | |
| 85 | frc equ IOBASE+18h ;Free Running Counter\r | |
| 86 | \r | |
| 87 | astc0l equ IOBASE+1Ah ;ASCI Time Constant Register 0\r | |
| 88 | astc0h equ IOBASE+1Bh ;\r | |
| 89 | astc1l equ IOBASE+1Ch ;ASCI Time Constant Register 1\r | |
| 90 | astc1h equ IOBASE+1Dh ;\r | |
| 91 | \r | |
| 92 | cmr equ IOBASE+1Eh ;Clock Mutiplier Register\r | |
| 93 | b2m X2CM,7 ;X2 Clock Multiplier\r | |
| 94 | b2m LNC,6 ;Low Noise Crystal\r | |
| 95 | \r | |
| 96 | ccr equ IOBASE+1Fh ;CPU Control Register\r | |
| 815c1735 | 97 | b2m NCD 7 ;No Clock Divide\r |
| a16ba2b0 L |
98 | \r |
| 99 | sar0l equ IOBASE+20h ;DMA Src Adr Register Channel 0\r | |
| 100 | sar0h equ IOBASE+21h ;\r | |
| 101 | sar0b equ IOBASE+22h ;\r | |
| 102 | dar0l equ IOBASE+23h ;DMA Dst Adr Register Channel 0\r | |
| 103 | dar0h equ IOBASE+24h ;\r | |
| 104 | dar0b equ IOBASE+25h ;\r | |
| 105 | bcr0l equ IOBASE+26h ;DMA Byte Count Register Channel 0\r | |
| 106 | bcr0h equ IOBASE+27h ;\r | |
| 107 | \r | |
| 108 | mar1l equ IOBASE+28h ;DMA Memory Address Register Channel 1\r | |
| 109 | mar1h equ IOBASE+29h ;\r | |
| 110 | mar1b equ IOBASE+2Ah ;\r | |
| 111 | iar1l equ IOBASE+2Bh ;DMA I/O Address Register Channel 1\r | |
| 112 | iar1h equ IOBASE+2Ch ;\r | |
| 113 | iar1b equ IOBASE+2Dh ;\r | |
| 114 | b2m ALTE,7 ;Alternating Chnnels\r | |
| 115 | b2m ALTC,6 ;Currently selected DMA Channel when Bit7=1\r | |
| 116 | b2m REQ1SEL2,2 ;\r | |
| 117 | b2m REQ1SEL1,1 ;\r | |
| 118 | b2m REQ1SEL0,0 ;\r | |
| 119 | \r | |
| 120 | bcr1l equ IOBASE+2Eh ;DMA Byte Count Register Channel 1\r | |
| 121 | bcr1h equ IOBASE+2Fh ;\r | |
| 122 | \r | |
| 123 | dstat equ IOBASE+30h ;DMA Status Register\r | |
| 124 | b2m DE1,7 ;DMA enable ch 1,0\r | |
| 125 | b2m DE0,6 ;\r | |
| 126 | b2m DWE1,5 ;DMA Enable Bit Write Enable 1,0\r | |
| 127 | b2m DWE0,4 ;\r | |
| 128 | b2m DIE1,3 ;DMA Interrupt Enable 1,0\r | |
| 129 | b2m DIE0,2 ;\r | |
| 130 | b2m DME,0 ;DMA Master enable\r | |
| 131 | \r | |
| 132 | dmode equ IOBASE+31h ;DMA Mode Register\r | |
| 133 | b2m DM1,5 ;Ch 0 Destination Mode 1,0\r | |
| 134 | b2m DM0,4 ;\r | |
| 135 | b2m SM1,3 ;Ch 0 Source Mode 1,0\r | |
| 136 | b2m SM0,2 ;\r | |
| 137 | b2m MMOD,1 ;Memory MODE select (0=cycle steel/1=burst)\r | |
| 138 | \r | |
| 139 | dcntl equ IOBASE+32h ;DMA/WAIT Control\r | |
| 140 | b2m MWI1,7 ;Memory Wait Insertion\r | |
| 141 | b2m MWI0,6 ;\r | |
| 142 | b2m IWI1,5 ;I/O Wait Insertion\r | |
| 143 | b2m IWI0,4 ;\r | |
| 144 | b2m DMS1,3 ;DREQi Select (Edge/Level)\r | |
| 145 | b2m DMS0,2 ;\r | |
| 146 | b2m DIMA1,1 ;DMA Ch1 I/O Memory Mode Select\r | |
| 147 | b2m DIMA0,0\r | |
| 148 | M_MWI equ M_MWI1 + M_MWI0\r | |
| 149 | M_IWI equ M_IWI1 + M_IWI0\r | |
| 150 | \r | |
| 151 | il equ IOBASE+33h ;Interrupt Vector Low Register\r | |
| 152 | itc equ IOBASE+34h ;INT/TRAP Control Register\r | |
| 153 | b2m TRAP,7 ;Trap\r | |
| 154 | b2m UFO,6 ;Unidentified Fetch Object\r | |
| 155 | b2m ITE2,2 ;/INT Enable 2,1,0\r | |
| 156 | b2m ITE1,1 ;\r | |
| 157 | b2m ITE0,0 ;\r | |
| 158 | \r | |
| 159 | rcr equ IOBASE+36h ;Refresh Control Register\r | |
| 160 | b2m REFE,7 ;Refresh Enable\r | |
| 161 | b2m REFW,6 ;Refresh Wait State\r | |
| 162 | b2m CYC1,1 ;Cycle select\r | |
| 163 | b2m CYC0,0 ;\r | |
| 164 | \r | |
| 165 | cbr equ IOBASE+38h ;MMU Common Base Register\r | |
| 166 | bbr equ IOBASE+39h ;MMU Bank Base Register\r | |
| 167 | cbar equ IOBASE+3Ah ;MMU Common/Bank Register\r | |
| 168 | \r | |
| 169 | omcr equ IOBASE+3Eh ;Operation Mode Control Register\r | |
| 170 | b2m M1E,7 ;M1 Enable\r | |
| 171 | b2m M1TE,6 ;M1 Temporary Enable\r | |
| 172 | b2m IOC,5 ;I/O Compatibility\r | |
| 173 | \r | |
| 174 | icr equ IOBASE+3Fh ;I/O Control Register\r | |
| 175 | b2m IOSTP,5 ;I/O Stop\r | |
| 176 | ;\r | |
| 177 | ; Interrupt Vectors\r | |
| 178 | ;\r | |
| 179 | \r | |
| 180 | IV$INT1 equ 0 ;/INT1 (highest priority)\r | |
| 181 | IV$INT2 equ 2 ;/INT2\r | |
| 182 | IV$PRT0 equ 4 ;PRT channel 0\r | |
| 183 | IV$PRT1 equ 6 ;PRT channel 1\r | |
| 184 | IV$DMA0 equ 8 ;DMA channel 0\r | |
| 185 | IV$DMA1 equ 10 ;DMA channel 1\r | |
| 186 | IV$CSIO equ 12 ;CSI/O\r | |
| 187 | IV$ASCI0 equ 14 ;ASCI channel 0\r | |
| 188 | IV$ASCI1 equ 16 ;ASCI channel 1 (lowest priority)\r | |
| 189 | \r | |
| 190 | .list\r | |
| 191 | \r |