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Commit | Line | Data |
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226d3221 L |
1 | .z80 ; for M80, ignored by SLR assembler\r |
2 | include z180reg.inc\r | |
3 | \r | |
4 | RUN_TPA equ 0\r | |
5 | \r | |
6 | UUNKNOWN equ 0 ;Unknown CPU\r | |
7 | U8080 equ 1 ;8080\r | |
8 | U8085 equ 2 ;8085\r | |
9 | UZ80 equ 3 ;Z80\r | |
10 | UX180 equ 4 ;HD64180 or higher\r | |
11 | UHD64180 equ 5 ;HD64180\r | |
12 | UZ80180 equ 6 ;Z80180\r | |
13 | UZ8S180 equ 7 ;Z8S180, Z8L180\r | |
14 | \r | |
15 | \r | |
16 | ;-------------------------------------------------------------------------------\r | |
17 | \r | |
18 | \r | |
19 | if RUN_TPA\r | |
20 | base equ 0100h\r | |
21 | else\r | |
22 | base equ 0\r | |
23 | endif\r | |
24 | \r | |
25 | \r | |
26 | aseg\r | |
27 | org base\r | |
28 | jp start\r | |
29 | \r | |
30 | done: db 0\r | |
31 | result: db 0\r | |
7535ca1b L |
32 | cycls: db 0\r |
33 | wstates:db 0\r | |
34 | \r | |
35 | ;-------------------------------------------------------------------------------\r | |
36 | cyctab:\r | |
37 | db 0 ;Unknown CPU\r | |
38 | db 20 ;8080\r | |
39 | db 20 ;8085\r | |
40 | db 21 ;Z80\r | |
41 | db 19 ;HD64180 or higher\r | |
42 | db 19 ;HD64180\r | |
43 | db 19 ;Z80180\r | |
44 | db 19 ;Z8S180, Z8L180\r | |
226d3221 | 45 | \r |
226d3221 L |
46 | ;-------------------------------------------------------------------------------\r |
47 | ; Check if register C exists. D holds mask of bit to test.\r | |
aea51b6c | 48 | ; return z, if register exists\r |
226d3221 L |
49 | \r |
50 | chk_reg:\r | |
aea51b6c L |
51 | in a,(c)\r |
52 | ld l,a\r | |
226d3221 | 53 | ; check, if register is changeable\r |
aea51b6c L |
54 | xor d ;\r |
55 | out (c),a\r | |
56 | in a,(c) ; get it back\r | |
57 | xor d\r | |
58 | out (c),l ; set register to original state\r | |
59 | cp l\r | |
226d3221 L |
60 | ret\r |
61 | \r | |
62 | ;-------------------------------------------------------------------------------\r | |
63 | ; Check CPU\r | |
64 | ;\r | |
65 | ;\r | |
66 | ; return:\r | |
67 | ; E = 0 Unknown\r | |
68 | ; E = 1 8080\r | |
69 | ; E = 2 8085\r | |
70 | ; E = 3 Z80\r | |
71 | ; E = 4 HD64180 or higher\r | |
72 | ; E = 5 HD64180\r | |
73 | ; E = 6 Z80180\r | |
74 | ; E = 7 Z8S180, Z8L180\r | |
75 | ;\r | |
76 | ;-------------------------------------------------------------------------------\r | |
77 | ; Registers only in Z180+, not in HD64180\r | |
78 | ; 3E OMCR\r | |
79 | ;\r | |
80 | ; Registers only in Z8S180/Z8L180\r | |
81 | ; 12 ASEXT0\r | |
82 | ; 13 ASEXT1\r | |
83 | ; 1A ASTC0L\r | |
84 | ; 1B ASTC0H\r | |
85 | ; 1C ASTC1L\r | |
86 | ; 1D ASTC1H\r | |
87 | ; 1E CMR\r | |
88 | ; 1F CCR\r | |
89 | ; 2D IAR1B\r | |
90 | ;\r | |
91 | ; Reserved registers\r | |
92 | ; 11\r | |
93 | ; 19\r | |
94 | ; 35\r | |
95 | ; 37\r | |
96 | ; 3B - 3D\r | |
97 | \r | |
98 | check:\r | |
99 | ld e,U8080 ; Init return val, assume 8080\r | |
100 | xor a\r | |
101 | dec a ; 00 --> 0FFH 8080/8085: even parity; Z80+: No overflow\r | |
102 | jp po,chk_z80 ; Z80+ if P/V flag reset\r | |
103 | \r | |
104 | ; The 8085 logical AND instructions always set the auxiliary flag ON.\r | |
105 | ; The 8080 logical AND instructions set the flag to reflect the\r | |
106 | ; logical OR of bit 3 of the values involved in the AND operation.\r | |
107 | ; (8080/8085 ASSEMBLY LANGUAGE PROGRAMMING MANUAL, 1977, 1978)\r | |
108 | \r | |
109 | xor a\r | |
110 | and a ; 8085 sets, 8080 resets half carry.\r | |
111 | daa ; A=06 (8085) or A=00 (8080)\r | |
112 | ret z\r | |
113 | inc e\r | |
114 | ret\r | |
115 | \r | |
116 | chk_z80:\r | |
117 | ld e,UZ80 ; Assume Z80\r | |
118 | daa ; Z80: 099H, x180+: 0F9H\r | |
119 | cp 99h ; Result on 180 type cpus is F9 here. Thanks Hitachi\r | |
120 | ret z\r | |
121 | inc e ; x180\r | |
122 | \r | |
123 | ; At least Hitachi HD64180\r | |
124 | ; Test differences in certain internal registers\r | |
125 | ; to determine the 180 variant.\r | |
aea51b6c | 126 | \r |
7535ca1b L |
127 | ld a,(wstates)\r |
128 | out0 (DCNTL),a\r | |
129 | out0 (RCR),b ;\r | |
130 | in0 a,(icr)\r | |
226d3221 | 131 | cp 01FH\r |
aea51b6c | 132 | jr z,icr_ok\r |
226d3221 L |
133 | \r |
134 | ;TODO: additional plausibility checks\r | |
135 | \r | |
aea51b6c | 136 | ret ; I/O registers not found\r |
226d3221 L |
137 | \r |
138 | ; Register (base) found.\r | |
139 | \r | |
aea51b6c | 140 | icr_ok:\r |
226d3221 | 141 | inc e ; HD64180\r |
aea51b6c | 142 | ld c,omcr ; Check, if CPU has OMCR register\r |
226d3221 L |
143 | ld d,M_IOC ;\r |
144 | call chk_reg ;\r | |
aea51b6c | 145 | ret nz ; Register does not exist. It's a HD64180\r |
226d3221 L |
146 | \r |
147 | inc e ; Z80180\r | |
aea51b6c | 148 | ld c,cmr ; Check, if CPU has CMR register\r |
226d3221 L |
149 | ld d,M_LNC ;\r |
150 | call chk_reg ;\r | |
aea51b6c | 151 | ret nz ; register does not exist. It's a Z80180\r |
226d3221 L |
152 | \r |
153 | inc e ; S180/L180 (class) detected.\r | |
226d3221 L |
154 | ret\r |
155 | \r | |
156 | ;-------------------------------------------------------------------------------\r | |
157 | \r | |
158 | start:\r | |
159 | ld sp,stack\r | |
aea51b6c | 160 | ld hl,done\r |
7535ca1b L |
161 | ld b,h\r |
162 | ld (hl),b\r | |
aea51b6c | 163 | inc hl\r |
7535ca1b | 164 | ld (hl),b\r |
226d3221 | 165 | call check\r |
7535ca1b L |
166 | ld hl,cyctab\r |
167 | ld d,h\r | |
168 | add hl,de\r | |
169 | ld a,(hl)\r | |
170 | ld hl,cycls\r | |
171 | ld (hl),a\r | |
172 | dec hl\r | |
226d3221 L |
173 | ld (hl),e\r |
174 | dec hl\r | |
175 | ld (hl),0ffH\r | |
1ffa84bd | 176 | out (040H),a\r |
7535ca1b L |
177 | ;808x Z80 Z180(0W) Z180(MaxW)\r |
178 | loop: ;---------------------------------\r | |
179 | in a,(050h) ;10 11 10 +3*3 19\r | |
180 | jp loop ;10 10 9 +3*3 18\r | |
181 | ;---------------------------------\r | |
182 | ;20 21 19 37\r | |
1ffa84bd | 183 | \r |
7535ca1b | 184 | ; jr loop ;-- 12 8 +2*3 14\r |
226d3221 | 185 | \r |
7535ca1b | 186 | rept 4\r |
226d3221 L |
187 | dw 0\r |
188 | endm\r | |
189 | stack:\r | |
190 | end\r | |
191 | \r | |
192 | ; vim:set ts=8 noet nowrap\r |