[z180-stamp.git] / avr / i2c.c


/* 
 * I2C (TWI) master interface. 
 */

#include "common.h"
#include <avr/interrupt.h>
#include <util/delay.h>
#include <string.h>

#include "config.h"
#include "timer.h"
#include "debug.h"
#include "i2c.h"

#define  DEBUG_I2C 0

#define debug_i2c(fmt, args...)			\
	debug_cond(DEBUG_I2C, fmt, ##args)


/* General TWI Master status codes */
#define TWI_START                  0x08  /* START has been transmitted */
#define TWI_REP_START              0x10  /* Repeated START has been transmitted */
#define TWI_ARB_LOST               0x38  /* Arbitration lost */

/* TWI Master Transmitter status codes */
#define TWI_MTX_ADR_ACK            0x18  /* SLA+W has been transmitted and ACK received */
#define TWI_MTX_ADR_NACK           0x20  /* SLA+W has been transmitted and NACK received */
#define TWI_MTX_DATA_ACK           0x28  /* Data byte has been transmitted and ACK received */
#define TWI_MTX_DATA_NACK          0x30  /* Data byte has been transmitted and NACK received */

/* TWI Master Receiver status codes */
#define TWI_MRX_ADR_ACK            0x40  /* SLA+R has been transmitted and ACK received */
#define TWI_MRX_ADR_NACK           0x48  /* SLA+R has been transmitted and NACK received */
#define TWI_MRX_DATA_ACK           0x50  /* Data byte has been received and ACK transmitted */
#define TWI_MRX_DATA_NACK          0x58  /* Data byte has been received and NACK transmitted */

/* TWI Miscellaneous status codes */
#define TWI_NO_STATE               0xF8  /* No relevant state information available */
#define TWI_BUS_ERROR              0x00  /* Bus error due to an illegal START or STOP condition */


/*
 * TWINT: TWI Interrupt Flag
 * TWEA:  TWI Enable Acknowledge Bit
 * TWSTA: TWI START Condition Bit
 * TWSTO: TWI STOP Condition Bit
 * TWEN:  TWI Enable Bit
 * TWIE:  TWI Interrupt Enable
 * 
 * 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)
 * 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|           (1<<TWEA)
 * 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)
 * 
 * default:
 * 	(1<<TWEN)|          (1<<TWINT)|           (1<<TWSTO)
 * 
 * Init:
 * 	(1<<TWEN)
 * 
 * start read/write:
 * 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
 * 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
 * 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
 * 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
 * 
 * wait ready:
 * 	 (1<<TWIE)|(1<<TWSTO)
 *
 *
 *
 *i2c_result	
 *
 *	0b10000000	Busy (Transmission in progress)
 *	0b01000000	Timeout
 *	0b00001000	Start transmitted 
 *	0b00000100	Slave acknowledged address
 *	0b00000010	Data byte(s) transmitted/received
 *	0b00000001	Transmission completed
 *
 *
 *----------------------------------------------------------------------
 */

#define TWI_C_DISABLE		0x00
#define TWI_C_ENABLE		(1<<TWEN)

 
 typedef struct i2c_msg_s {
	uint8_t stat;
 #define XMIT_DONE	(1<<0)
 #define DATA_ACK	(1<<1)
 #define ADDR_ACK	(1<<2)
 #define START		(1<<3)
 #define TIMEOUT	(1<<6)
 #define BUSY		(1<<7)
	uint8_t idx;
	uint8_t len;
	uint8_t buf[CONFIG_SYS_I2C_BUFSIZE];
} i2c_msg_t;

static volatile i2c_msg_t xmit;

ISR(TWI_vect)
{
	uint8_t tmp_stat;
	uint8_t tmp_idx;
	uint8_t next_twcr;
	uint8_t n;

	tmp_idx = xmit.idx;
	tmp_stat = xmit.stat;

	uint8_t twsr = TWSR;
		
	switch (twsr & 0xf8) {

	case TWI_START:
	case TWI_REP_START:
		tmp_stat = BUSY | START;
		tmp_idx = 0;			/* reset xmit_buf index */

		if (tmp_idx < xmit.len) {		/* all bytes transmited? */
			TWDR = xmit.buf[tmp_idx];
			++tmp_idx;
			next_twcr = (1<<TWEN)|(1<<TWIE)|(1<<TWINT);
		} else {
			tmp_stat |= XMIT_DONE;
			tmp_stat &= ~BUSY;
			next_twcr = (1<<TWEN)|(0<<TWIE)|(1<<TWINT)|(1<<TWSTO);
		}
		break;

	case TWI_MTX_ADR_ACK:
	case TWI_MTX_DATA_ACK:
		if ((twsr&0xf8) == TWI_MTX_ADR_ACK)
			tmp_stat |= ADDR_ACK;
		else
			tmp_stat |= DATA_ACK;

		if (tmp_idx < xmit.len) {		/* all bytes transmited? */
			TWDR = xmit.buf[tmp_idx];
			++tmp_idx;
			next_twcr = (1<<TWEN)|(1<<TWIE)|(1<<TWINT);
		} else {
			tmp_stat |= XMIT_DONE;
			tmp_stat &= ~BUSY;
			next_twcr = (1<<TWEN)|(0<<TWIE)|(1<<TWINT)|(1<<TWSTO);
		}
		break;

	case TWI_MTX_DATA_NACK:
		tmp_stat |= XMIT_DONE;
		tmp_stat &= ~BUSY;
		next_twcr = (1<<TWEN)|(0<<TWIE)|(1<<TWINT)|(1<<TWSTO);
		break;

	case TWI_MRX_DATA_ACK:
		xmit.buf[tmp_idx] = TWDR;
		++tmp_idx;
		/* fall thru */
	case TWI_MRX_ADR_ACK:
		if ((twsr&0xf8) == TWI_MRX_ADR_ACK)
			tmp_stat |= ADDR_ACK;
		else
			tmp_stat |= DATA_ACK;

		n = xmit.len-1;
		if (tmp_idx < n) {
			next_twcr = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA);
		} else {
			next_twcr = (1<<TWEN)|(1<<TWIE)|(1<<TWINT);
		}
		break;

	case TWI_MRX_DATA_NACK:
		tmp_stat |= ADDR_ACK | DATA_ACK;

		xmit.buf[tmp_idx] = TWDR;
		++tmp_idx;
		/* fall thru */
	default:
		tmp_stat &= ~BUSY;
		next_twcr = (1<<TWEN)|(0<<TWIE)|(1<<TWINT)|(1<<TWSTO);
		break;
	}

	xmit.stat = tmp_stat;
	xmit.idx = tmp_idx;

	debug_i2c("|%02x", twsr);
	TWCR = next_twcr;
}


/*------------------------------------------------------------------*/

static uint8_t twps;
static uint8_t twbr;


static void _init(void)
{
	xmit.stat = 0;

	/* Disable TWI, disable TWI interrupt. */
	/* (Reset TWI hardware state machine.) */
	TWCR = TWI_C_DISABLE;
	_delay_us(5);
#if DEBUG_I2C
	memset((void *) xmit.buf, 0xdf, sizeof(xmit.buf));
#endif

	TWDR = 0xff;
	TWBR = twbr;
	TWSR = twps & 0x03;
	TWCR = TWI_C_ENABLE;
}

void i2c_init(uint32_t speed)
{
	twps = 0;
	uint32_t tmp_twbr = F_CPU /2 / speed - 8;
	
	while (tmp_twbr > 255) {
		tmp_twbr >>= 4;
		twps += 1;
	}
	debug_cond((twps > 3), "*** TWCLK too low: %lu Hz\n", speed);

	twbr = (uint8_t) tmp_twbr;
	_init();
}


int_fast8_t i2c_waitready(void)
{
	uint32_t timer = get_timer(0);
	uint8_t timeout = 0;
	
	do {
		if (get_timer(timer) >= 30) {
			timeout = TIMEOUT;
			_init();
		}
	} while ((TWCR & ((1<<TWIE)|(1<<TWSTO))) != 0 && !timeout);

	xmit.stat |= timeout;

#if DEBUG_I2C
	dump_ram((uint8_t *) &xmit, 4, "=== i2c_wait ready: (done)");
	_delay_ms(30);
#endif	
	return xmit.stat;
}

static
int i2c_send(uint8_t chip, uint16_t addr, uint8_t alen, uint8_t *buffer, int8_t len)
{
	uint8_t i, n;
	uint8_t rc;

	rc = i2c_waitready();
	if ((rc & (BUSY | TIMEOUT)) != 0)
		return rc;

	xmit.stat = BUSY;
	xmit.buf[0] = chip<<1;
	for (i = 1; i < alen+1; i++) {
		xmit.buf[i] = (uint8_t) addr;
		addr >>= 8;
	}
	for (n = len + i; i < n; i++)
		xmit.buf[i] = *buffer++;
	xmit.len = i;
	
#if DEBUG_I2C
	dump_ram((uint8_t *) &xmit, 0x20, "=== i2c_send");
	_delay_ms(30);
#endif	
	/* Enable TWI, TWI int and initiate start condition */
	TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA);

	rc = xmit.stat;

	return rc;
}

static
int i2c_recv(uint8_t chip, uint8_t *buffer, int8_t len)
{
	uint8_t rc;

	rc = i2c_waitready();
	if ((rc & (BUSY | TIMEOUT)) != 0)
		return rc;

	xmit.stat = BUSY;
	xmit.len = len + 1;
	xmit.buf[0] = (chip<<1) | 1;

#if DEBUG_I2C
	dump_ram((uint8_t *) &xmit, 0x20, "=== i2c_recv: before start");
	_delay_ms(30);
#endif
	/* Enable TWI, TWI int and initiate start condition */
	TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA);
	rc = i2c_waitready();

#if DEBUG_I2C
	dump_ram((uint8_t *) &xmit, 0x20, "=== i2c_recv: after completion");
	_delay_ms(30);
#endif
	if (rc & DATA_ACK) {
		/* at least 1 byte received */
		for (uint8_t i=1, n=xmit.idx; i < n; i++)
			*buffer++ = xmit.buf[i];
	}

	return rc;
}

/*
 * Read/Write interface:
 *   chip:    I2C chip address, range 0..127
 *   addr:    Memory (register) address within the chip
 *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
 *              memories, 0 for register type devices with only one
 *              register)
 *   buffer:  Where to read/write the data
 *   len:     How many bytes to read/write
 *
 *   Returns: 0 on success, not 0 on failure
 */

int i2c_write(uint8_t chip, unsigned int addr, uint_fast8_t alen,
				uint8_t *buffer, uint_fast8_t len)
{
	int rc;
	
	if ((alen > 2) || (1 + alen + len > CONFIG_SYS_I2C_BUFSIZE)) {
		debug("** i2c_write: buffer overflow, alen: %u, len: %u\n",
			alen, len);
		return -1;
	}
	
	i2c_send(chip, addr, alen, buffer, len);
	rc = i2c_waitready();

	return (rc & XMIT_DONE) != 0;
}

int i2c_read(uint8_t chip, unsigned int addr, uint_fast8_t alen,
				uint8_t *buffer, uint_fast8_t len)
{
	int rc;

	if ((alen > 2) || (1 + len > CONFIG_SYS_I2C_BUFSIZE)) {
		debug("** i2c_read: parameter error: alen: %u, len: %u\n",
			alen, len);
		return -1;
	}
	
	if (alen != 0) {
		i2c_send(chip, addr, alen, NULL, 0);
	}	
	rc = i2c_recv(chip, buffer, len);

	return !((rc & (XMIT_DONE|DATA_ACK)) == (XMIT_DONE|DATA_ACK));
}
Commit	Line	Data
61b0cfe9 L	1
	2	/*
	3	* I2C (TWI) master interface.
	4	*/
	5
	6	#include "common.h"
	7	#include <avr/interrupt.h>
	8	#include <util/delay.h>
	9	#include <string.h>
	10
	11	#include "config.h"
	12	#include "timer.h"
	13	#include "debug.h"
	14	#include "i2c.h"
	15
f14850db L	16	#define DEBUG_I2C 0
	17
	18	#define debug_i2c(fmt, args...) \
	19	debug_cond(DEBUG_I2C, fmt, ##args)
	20
61b0cfe9 L	21
	22	/* General TWI Master status codes */
	23	#define TWI_START 0x08 /* START has been transmitted */
	24	#define TWI_REP_START 0x10 /* Repeated START has been transmitted */
	25	#define TWI_ARB_LOST 0x38 /* Arbitration lost */
	26
	27	/* TWI Master Transmitter status codes */
	28	#define TWI_MTX_ADR_ACK 0x18 /* SLA+W has been transmitted and ACK received */
	29	#define TWI_MTX_ADR_NACK 0x20 /* SLA+W has been transmitted and NACK received */
	30	#define TWI_MTX_DATA_ACK 0x28 /* Data byte has been transmitted and ACK received */
	31	#define TWI_MTX_DATA_NACK 0x30 /* Data byte has been transmitted and NACK received */
	32
	33	/* TWI Master Receiver status codes */
	34	#define TWI_MRX_ADR_ACK 0x40 /* SLA+R has been transmitted and ACK received */
	35	#define TWI_MRX_ADR_NACK 0x48 /* SLA+R has been transmitted and NACK received */
	36	#define TWI_MRX_DATA_ACK 0x50 /* Data byte has been received and ACK transmitted */
	37	#define TWI_MRX_DATA_NACK 0x58 /* Data byte has been received and NACK transmitted */
	38
	39	/* TWI Miscellaneous status codes */
	40	#define TWI_NO_STATE 0xF8 /* No relevant state information available */
	41	#define TWI_BUS_ERROR 0x00 /* Bus error due to an illegal START or STOP condition */
	42
	43
	44	/*
	45	* TWINT: TWI Interrupt Flag
	46	* TWEA: TWI Enable Acknowledge Bit
	47	* TWSTA: TWI START Condition Bit
	48	* TWSTO: TWI STOP Condition Bit
	49	* TWEN: TWI Enable Bit
	50	* TWIE: TWI Interrupt Enable
	51	*
	52	* (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)
	53	* (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\| (1<<TWEA)
	54	* (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)
	55	*
	56	* default:
	57	* (1<<TWEN)\| (1<<TWINT)\| (1<<TWSTO)
	58	*
	59	* Init:
	60	* (1<<TWEN)
	61	*
	62	* start read/write:
	63	* (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
	64	* (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
	65	* (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
	66	* (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
	67	*
	68	* wait ready:
	69	* (1<<TWIE)\|(1<<TWSTO)
	70	*
	71	*
	72	*
	73	*i2c_result
	74	*
	75	* 0b10000000 Busy (Transmission in progress)
	76	* 0b01000000 Timeout
	77	* 0b00001000 Start transmitted
	78	* 0b00000100 Slave acknowledged address
	79	* 0b00000010 Data byte(s) transmitted/received
	80	* 0b00000001 Transmission completed
	81	*
	82	*
	83	*----------------------------------------------------------------------
	84	*/
85
86	#define TWI_C_DISABLE 0x00
87	#define TWI_C_ENABLE (1<<TWEN)
88
89
90
91	typedef struct i2c_msg_s {
92	uint8_t stat;
93	#define XMIT_DONE (1<<0)
94	#define DATA_ACK (1<<1)
95	#define ADDR_ACK (1<<2)
96	#define START (1<<3)
97	#define TIMEOUT (1<<6)
98	#define BUSY (1<<7)
99	uint8_t idx;
100	uint8_t len;
101	uint8_t buf[CONFIG_SYS_I2C_BUFSIZE];
102	} i2c_msg_t;
103
35e9ec0c	104	static volatile i2c_msg_t xmit;
61b0cfe9 L	105
	106	ISR(TWI_vect)
	107	{
35e9ec0c	108	uint8_t tmp_stat;
61b0cfe9	109	uint8_t tmp_idx;
35e9ec0c L	110	uint8_t next_twcr;
	111	uint8_t n;
	112
	113	tmp_idx = xmit.idx;
	114	tmp_stat = xmit.stat;
61b0cfe9 L	115
	116	uint8_t twsr = TWSR;
	117
	118	switch (twsr & 0xf8) {
	119
	120	case TWI_START:
	121	case TWI_REP_START:
35e9ec0c L	122	tmp_stat = BUSY \| START;
35e9ec0c L	123	tmp_idx = 0; /* reset xmit_buf index */
61b0cfe9	124
61b0cfe9 L	125	if (tmp_idx < xmit.len) { /* all bytes transmited? */
61b0cfe9 L	126	TWDR = xmit.buf[tmp_idx];
35e9ec0c	127	++tmp_idx;
61b0cfe9 L	128	next_twcr = (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT);
61b0cfe9 L	129	} else {
35e9ec0c L	130	tmp_stat \|= XMIT_DONE;
35e9ec0c L	131	tmp_stat &= ~BUSY;
61b0cfe9 L	132	next_twcr = (1<<TWEN)\|(0<<TWIE)\|(1<<TWINT)\|(1<<TWSTO);
	133	}
	134	break;
	135
	136	case TWI_MTX_ADR_ACK:
61b0cfe9	137	case TWI_MTX_DATA_ACK:
85787726 L	138	if ((twsr&0xf8) == TWI_MTX_ADR_ACK)
	139	tmp_stat \|= ADDR_ACK;
	140	else
	141	tmp_stat \|= DATA_ACK;
61b0cfe9	142
61b0cfe9 L	143	if (tmp_idx < xmit.len) { /* all bytes transmited? */
61b0cfe9 L	144	TWDR = xmit.buf[tmp_idx];
35e9ec0c	145	++tmp_idx;
61b0cfe9 L	146	next_twcr = (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT);
61b0cfe9 L	147	} else {
35e9ec0c L	148	tmp_stat \|= XMIT_DONE;
35e9ec0c L	149	tmp_stat &= ~BUSY;
61b0cfe9 L	150	next_twcr = (1<<TWEN)\|(0<<TWIE)\|(1<<TWINT)\|(1<<TWSTO);
61b0cfe9 L	151	}
61b0cfe9 L	152	break;
	153
	154	case TWI_MTX_DATA_NACK:
35e9ec0c L	155	tmp_stat \|= XMIT_DONE;
35e9ec0c L	156	tmp_stat &= ~BUSY;
61b0cfe9 L	157	next_twcr = (1<<TWEN)\|(0<<TWIE)\|(1<<TWINT)\|(1<<TWSTO);
	158	break;
	159
61b0cfe9	160	case TWI_MRX_DATA_ACK:
61b0cfe9	161	xmit.buf[tmp_idx] = TWDR;
35e9ec0c	162	++tmp_idx;
85787726 L	163	/* fall thru */
	164	case TWI_MRX_ADR_ACK:
	165	if ((twsr&0xf8) == TWI_MRX_ADR_ACK)
	166	tmp_stat \|= ADDR_ACK;
	167	else
	168	tmp_stat \|= DATA_ACK;
	169
35e9ec0c L	170	n = xmit.len-1;
35e9ec0c L	171	if (tmp_idx < n) {
61b0cfe9 L	172	next_twcr = (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWEA);
61b0cfe9 L	173	} else {
61b0cfe9 L	174	next_twcr = (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT);
	175	}
	176	break;
	177
	178	case TWI_MRX_DATA_NACK:
35e9ec0c	179	tmp_stat \|= ADDR_ACK \| DATA_ACK;
61b0cfe9	180
61b0cfe9	181	xmit.buf[tmp_idx] = TWDR;
35e9ec0c	182	++tmp_idx;
61b0cfe9	183	/* fall thru */
61b0cfe9	184	default:
35e9ec0c	185	tmp_stat &= ~BUSY;
61b0cfe9 L	186	next_twcr = (1<<TWEN)\|(0<<TWIE)\|(1<<TWINT)\|(1<<TWSTO);
	187	break;
	188	}
	189
35e9ec0c L	190	xmit.stat = tmp_stat;
	191	xmit.idx = tmp_idx;
	192
f14850db	193	debug_i2c("\|%02x", twsr);
61b0cfe9 L	194	TWCR = next_twcr;
	195	}
	196
	197
	198	/------------------------------------------------------------------/
	199
	200	static uint8_t twps;
	201	static uint8_t twbr;
	202
	203
	204	static void _init(void)
	205	{
	206	xmit.stat = 0;
61b0cfe9 L	207
	208	/* Disable TWI, disable TWI interrupt. */
	209	/* (Reset TWI hardware state machine.) */
	210	TWCR = TWI_C_DISABLE;
	211	_delay_us(5);
f14850db	212	#if DEBUG_I2C
35e9ec0c L	213	memset((void *) xmit.buf, 0xdf, sizeof(xmit.buf));
35e9ec0c L	214	#endif
61b0cfe9	215
61b0cfe9	216	TWDR = 0xff;
35e9ec0c L	217	TWBR = twbr;
	218	TWSR = twps & 0x03;
	219	TWCR = TWI_C_ENABLE;
61b0cfe9 L	220	}
	221
	222	void i2c_init(uint32_t speed)
	223	{
	224	twps = 0;
35e9ec0c	225	uint32_t tmp_twbr = F_CPU /2 / speed - 8;
61b0cfe9	226
35e9ec0c L	227	while (tmp_twbr > 255) {
35e9ec0c L	228	tmp_twbr >>= 4;
61b0cfe9 L	229	twps += 1;
61b0cfe9 L	230	}
35e9ec0c L	231	debug_cond((twps > 3), "*** TWCLK too low: %lu Hz\n", speed);
	232
	233	twbr = (uint8_t) tmp_twbr;
61b0cfe9 L	234	_init();
	235	}
	236
	237
	238	int_fast8_t i2c_waitready(void)
	239	{
	240	uint32_t timer = get_timer(0);
	241	uint8_t timeout = 0;
	242
	243	do {
	244	if (get_timer(timer) >= 30) {
	245	timeout = TIMEOUT;
	246	_init();
	247	}
	248	} while ((TWCR & ((1<<TWIE)\|(1<<TWSTO))) != 0 && !timeout);
	249
	250	xmit.stat \|= timeout;
	251
f14850db	252	#if DEBUG_I2C
61b0cfe9 L	253	dump_ram((uint8_t *) &xmit, 4, "=== i2c_wait ready: (done)");
	254	_delay_ms(30);
	255	#endif
	256	return xmit.stat;
	257	}
	258
f14850db	259	static
61b0cfe9 L	260	int i2c_send(uint8_t chip, uint16_t addr, uint8_t alen, uint8_t *buffer, int8_t len)
	261	{
	262	uint8_t i, n;
	263	uint8_t rc;
	264
	265	rc = i2c_waitready();
	266	if ((rc & (BUSY \| TIMEOUT)) != 0)
	267	return rc;
	268
	269	xmit.stat = BUSY;
	270	xmit.buf[0] = chip<<1;
	271	for (i = 1; i < alen+1; i++) {
	272	xmit.buf[i] = (uint8_t) addr;
	273	addr >>= 8;
	274	}
	275	for (n = len + i; i < n; i++)
	276	xmit.buf[i] = *buffer++;
	277	xmit.len = i;
	278
f14850db	279	#if DEBUG_I2C
61b0cfe9 L	280	dump_ram((uint8_t *) &xmit, 0x20, "=== i2c_send");
	281	_delay_ms(30);
	282	#endif
	283	/* Enable TWI, TWI int and initiate start condition */
	284	TWCR = (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA);
	285
	286	rc = xmit.stat;
	287
	288	return rc;
	289	}
	290
f14850db	291	static
61b0cfe9 L	292	int i2c_recv(uint8_t chip, uint8_t *buffer, int8_t len)
	293	{
	294	uint8_t rc;
	295
	296	rc = i2c_waitready();
	297	if ((rc & (BUSY \| TIMEOUT)) != 0)
	298	return rc;
	299
	300	xmit.stat = BUSY;
	301	xmit.len = len + 1;
	302	xmit.buf[0] = (chip<<1) \| 1;
	303
f14850db	304	#if DEBUG_I2C
61b0cfe9 L	305	dump_ram((uint8_t *) &xmit, 0x20, "=== i2c_recv: before start");
	306	_delay_ms(30);
	307	#endif
	308	/* Enable TWI, TWI int and initiate start condition */
	309	TWCR = (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA);
	310	rc = i2c_waitready();
	311
f14850db	312	#if DEBUG_I2C
61b0cfe9 L	313	dump_ram((uint8_t *) &xmit, 0x20, "=== i2c_recv: after completion");
	314	_delay_ms(30);
	315	#endif
	316	if (rc & DATA_ACK) {
	317	/* at least 1 byte received */
	318	for (uint8_t i=1, n=xmit.idx; i < n; i++)
	319	*buffer++ = xmit.buf[i];
	320	}
	321
	322	return rc;
	323	}
	324
	325	/*
	326	* Read/Write interface:
	327	* chip: I2C chip address, range 0..127
	328	* addr: Memory (register) address within the chip
	329	* alen: Number of bytes to use for addr (typically 1, 2 for larger
	330	* memories, 0 for register type devices with only one
	331	* register)
	332	* buffer: Where to read/write the data
	333	* len: How many bytes to read/write
	334	*
	335	* Returns: 0 on success, not 0 on failure
	336	*/
	337
	338	int i2c_write(uint8_t chip, unsigned int addr, uint_fast8_t alen,
	339	uint8_t *buffer, uint_fast8_t len)
	340	{
	341	int rc;
	342
	343	if ((alen > 2) \|\| (1 + alen + len > CONFIG_SYS_I2C_BUFSIZE)) {
	344	debug("** i2c_write: buffer overflow, alen: %u, len: %u\n",
	345	alen, len);
	346	return -1;
	347	}
	348
	349	i2c_send(chip, addr, alen, buffer, len);
	350	rc = i2c_waitready();
61b0cfe9 L	351
	352	return (rc & XMIT_DONE) != 0;
	353	}
	354
	355	int i2c_read(uint8_t chip, unsigned int addr, uint_fast8_t alen,
	356	uint8_t *buffer, uint_fast8_t len)
	357	{
	358	int rc;
	359
	360	if ((alen > 2) \|\| (1 + len > CONFIG_SYS_I2C_BUFSIZE)) {
	361	debug("** i2c_read: parameter error: alen: %u, len: %u\n",
	362	alen, len);
	363	return -1;
	364	}
	365
	366	if (alen != 0) {
	367	i2c_send(chip, addr, alen, NULL, 0);
	368	}
	369	rc = i2c_recv(chip, buffer, len);
61b0cfe9 L	370
	371	return !((rc & (XMIT_DONE\|DATA_ACK)) == (XMIT_DONE\|DATA_ACK));
	372	}
	373
	374
	375