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e64eba00 L |
1 | /* |
2 | */ | |
3 | ||
e64eba00 L |
4 | |
5 | #include <libopencmsis/core_cm3.h> | |
6 | #include <libopencm3/cm3/nvic.h> | |
7 | #include <libopencm3/cm3/systick.h> | |
8 | #include <libopencm3/stm32/rtc.h> | |
e64eba00 L |
9 | #include <libopencm3/stm32/rcc.h> |
10 | #include <libopencm3/stm32/gpio.h> | |
11 | #include <libopencm3/stm32/timer.h> | |
12 | ||
64045ba0 L |
13 | #include <stdio.h> |
14 | ||
e64eba00 L |
15 | #define ODR 0x0c |
16 | #define IDR 0x08 | |
17 | ||
18 | ||
6b81b39f L |
19 | #include "debug.h" |
20 | #include "serial.h" | |
e64eba00 | 21 | #include "z80-if.h" |
f4d5b4fe | 22 | #include "../z180/hdrom.h" |
e64eba00 | 23 | |
6b81b39f | 24 | #define ESCCHAR ('^'-0x40) |
e64eba00 L |
25 | |
26 | #define S_10MS_TO (1<<0) | |
27 | ||
28 | /* | |
29 | * LED Connections | |
30 | */ | |
31 | ||
32 | #define LED_PORT GPIOC | |
33 | #define LED_BLUE_PIN GPIO8 | |
34 | #define BLUE 8 | |
35 | #define LED_GREEN_PIN GPIO9 | |
36 | #define GREEN 9 | |
37 | ||
38 | ||
39 | #define LED_BLUE_ON() BBIO_PERIPH(LED_PORT+ODR, BLUE) = 1 | |
40 | #define LED_BLUE_OFF() BBIO_PERIPH(LED_PORT+ODR, BLUE) = 0 | |
41 | #define LED_BLUE_TOGGLE() BBIO_PERIPH(LED_PORT+ODR, BLUE) = !BBIO_PERIPH(LED_PORT+ODR, BLUE) | |
42 | ||
43 | #define LED_GREEN_ON() BBIO_PERIPH(LED_PORT+ODR, GREEN) = 1 | |
44 | #define LED_GREEN_OFF() BBIO_PERIPH(LED_PORT+ODR, GREEN) = 0 | |
45 | #define LED_GREEN_TOGGLE() BBIO_PERIPH(LED_PORT+ODR, GREEN) = !BBIO_PERIPH(LED_PORT+ODR, GREEN) | |
46 | ||
47 | ||
48 | /* | |
49 | * Button connections | |
50 | */ | |
51 | ||
52 | //BBIO_PERIPH(GPIOA+IDR, 0); | |
53 | ||
54 | #define KEY_PORT GPIOA_IDR | |
55 | #define KEY0 GPIO0 | |
56 | //#define KEY1 GPIO1 | |
57 | //#define KEY2 GPIO2 | |
58 | ||
59 | #define REPEAT_MASK KEY0 // repeat: key0 | |
60 | #define REPEAT_START 100 // after 1s | |
61 | #define REPEAT_NEXT 20 // every 200ms | |
62 | ||
63 | ||
64 | typedef enum { | |
65 | NOTHING, PULSE, BLINK1, BLINK2 | |
66 | } LED_MODE; | |
67 | ||
68 | typedef struct { | |
69 | uint8_t mode; | |
70 | uint8_t ontime, offtime; | |
71 | } led_stat_t; | |
72 | ||
73 | volatile uint8_t led_timer[2]; | |
74 | led_stat_t led_stat[2]; | |
75 | ||
76 | volatile int timeout_1s; | |
77 | volatile uint32_t Stat; | |
78 | ||
79 | ||
80 | /*--------------------------------------------------------------------------*/ | |
81 | ||
82 | ||
83 | static void clock_setup(void) | |
84 | { | |
0d318092 L |
85 | //rcc_clock_setup_in_hse_8mhz_out_24mhz(); |
86 | rcc_clock_setup_in_hsi_out_24mhz(); | |
e64eba00 L |
87 | |
88 | /* Enable clocks for: | |
89 | GPIO port A (for GPIO_USART1_TX and Button) | |
90 | GPIO port C (LEDs) | |
91 | USART1 | |
92 | TIM16 (RST-Pin) | |
0d318092 | 93 | TIM1 (IOCS1) |
e64eba00 L |
94 | */ |
95 | rcc_peripheral_enable_clock(&RCC_APB2ENR, | |
96 | RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | |
97 | | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | |
98 | | RCC_APB2ENR_USART1EN | RCC_APB2ENR_AFIOEN | |
99 | | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM16EN); | |
100 | /* Enable clocks for: | |
101 | TIM3 | |
102 | */ | |
103 | rcc_peripheral_enable_clock(&RCC_APB1ENR, | |
104 | RCC_APB1ENR_TIM3EN); | |
105 | ||
106 | /* Enable clocks for: | |
0d318092 | 107 | DMA1 |
e64eba00 L |
108 | */ |
109 | rcc_peripheral_enable_clock(&RCC_AHBENR, | |
110 | RCC_AHBENR_DMA1EN); | |
111 | } | |
112 | ||
113 | static void systick_setup(void) | |
114 | { | |
115 | /* SysTick interrupt every N clock pulses: set reload to N-1 */ | |
116 | STK_RVR = 24000000/1000 - 1; | |
117 | ||
118 | /* Set source to core clock, enable int and start counting. */ | |
119 | STK_CSR = STK_CSR_CLKSOURCE_AHB | STK_CSR_TICKINT | STK_CSR_ENABLE; | |
120 | } | |
121 | ||
122 | #if 0 | |
123 | static void nvic_setup(void) | |
124 | { | |
125 | // nvic_enable_irq(NVIC_RTC_IRQ); | |
126 | // nvic_set_priority(NVIC_RTC_IRQ, 1); | |
127 | } | |
128 | #endif | |
129 | ||
130 | static void tim3_setup(void) | |
131 | { | |
132 | TIM3_CR1 = TIM_CR1_CMS_EDGE | TIM_CR1_DIR_UP; | |
133 | ||
134 | TIM3_CCMR2 = 0 | |
135 | | TIM_CCMR2_OC4M_FORCE_LOW | |
136 | /* | TIM_CCMR2_OC4M_FORCE_HIGH */ | |
137 | /* | TIM_CCMR2_OC4M_PWM2 */ | |
138 | ||
139 | /* | TIM_CCMR2_OC4PE */ | |
140 | /* | TIM_CCMR2_OC4FE */ | |
141 | | TIM_CCMR2_CC4S_OUT; | |
142 | ||
143 | TIM3_CCER = TIM_CCER_CC4E | |
144 | | TIM_CCER_CC4P; | |
145 | ||
146 | TIM3_ARR = 48; /* default */ | |
147 | TIM3_CCR4 = 1; /* */ | |
148 | } | |
149 | ||
150 | static void gpio_setup(void) | |
151 | { | |
152 | ||
153 | /* Disable JTAG-DP, but leave SW-DP Enabled. (free PA15, PB3, PB4) | |
154 | Remap SPI1 to PB3, PB4, PB5 and PA15. | |
155 | Remap TIM3 (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) | |
0d318092 | 156 | Port D0/Port D1 mapping on OSC_IN/OSC_OUT |
e64eba00 L |
157 | */ |
158 | gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON, | |
0d318092 L |
159 | AFIO_MAPR_SPI1_REMAP |
160 | | AFIO_MAPR_TIM3_REMAP_FULL_REMAP | |
161 | | AFIO_MAPR_PD01_REMAP); | |
e64eba00 L |
162 | |
163 | /* LEDs and User Button. */ | |
164 | gpio_set_mode(LED_PORT, GPIO_MODE_OUTPUT_2_MHZ, | |
165 | GPIO_CNF_OUTPUT_PUSHPULL, LED_BLUE_PIN); | |
166 | gpio_set_mode(LED_PORT, GPIO_MODE_OUTPUT_10_MHZ, | |
167 | GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, LED_GREEN_PIN); | |
168 | gpio_set_mode(GPIOA, GPIO_MODE_INPUT, | |
169 | GPIO_CNF_INPUT_FLOAT, GPIO0); | |
170 | } | |
171 | ||
172 | ||
e64eba00 L |
173 | /*--------------------------------------------------------------------------*/ |
174 | ||
175 | void delay_systicks(int ticks) | |
176 | { | |
177 | int start, stop, now; | |
178 | ||
179 | start = STK_CVR; | |
180 | stop = start - ticks; | |
181 | if (stop < 0) { | |
182 | stop += STK_RVR; | |
183 | do { | |
184 | now = STK_CVR; | |
185 | } while ((now > stop) || (now <= start)); | |
186 | } else { | |
187 | do { | |
188 | now = STK_CVR; | |
189 | } while ((now > stop) && (now <= start)); | |
190 | } | |
191 | } | |
192 | ||
193 | ||
194 | /*--------------------------------------------------------------------------*/ | |
195 | ||
196 | static void led_toggle(uint8_t lednr) { | |
197 | if (lednr == 0) | |
198 | LED_BLUE_TOGGLE(); | |
199 | else if (lednr == 1) | |
200 | LED_GREEN_TOGGLE(); | |
201 | } | |
202 | ||
203 | static void led_on(uint8_t lednr) { | |
204 | if (lednr == 0) | |
205 | LED_BLUE_ON(); | |
206 | else if (lednr == 1) | |
207 | LED_GREEN_ON(); | |
208 | } | |
209 | ||
210 | static void led_off(uint8_t lednr) { | |
211 | if (lednr == 0) | |
212 | LED_BLUE_OFF(); | |
213 | else if (lednr == 1) | |
214 | LED_GREEN_OFF(); | |
215 | } | |
216 | ||
217 | static uint8_t led_is_on(uint8_t lednr) { | |
218 | if (lednr == 0) | |
219 | return BBIO_PERIPH(LED_PORT+ODR, BLUE); | |
220 | else if (lednr == 1) | |
221 | return BBIO_PERIPH(LED_PORT+ODR, GREEN); | |
222 | else | |
223 | return 0; | |
224 | } | |
225 | ||
226 | static void ledset(uint8_t lednr, uint8_t what, uint8_t len) { | |
227 | ||
228 | led_stat[lednr].mode = what; | |
229 | switch (what) { | |
230 | case PULSE: | |
231 | led_stat[lednr].ontime = len; | |
232 | led_stat[lednr].offtime = 0; | |
233 | led_timer[lednr] = len; | |
234 | led_on(lednr); | |
235 | break; | |
236 | case BLINK1: | |
237 | case BLINK2: | |
238 | if (what == BLINK1) | |
239 | led_stat[lednr].offtime = 100 - len; | |
240 | else | |
241 | led_stat[lednr].offtime = 200 - len; | |
242 | led_stat[lednr].ontime = len; | |
243 | led_timer[lednr] = len; | |
244 | led_on(lednr); | |
245 | break; | |
246 | default: | |
247 | break; | |
248 | } | |
249 | } | |
250 | ||
251 | /*--------------------------------------------------------------------------*/ | |
252 | ||
253 | static volatile uint16_t key_state, | |
254 | key_press, // key press detect | |
255 | key_rpt; // key long press and repeat | |
256 | ||
257 | ||
258 | static uint16_t get_key_press(uint16_t key_mask) { | |
259 | __disable_irq(); | |
260 | // read and clear atomic ! | |
261 | key_mask &= key_press; // read key(s) | |
262 | key_press ^= key_mask; // clear key(s) | |
263 | __enable_irq(); | |
264 | return key_mask; | |
265 | } | |
266 | ||
6b81b39f | 267 | /* |
e64eba00 L |
268 | static uint16_t get_key_rpt(uint16_t key_mask) { |
269 | __disable_irq(); | |
270 | // read and clear atomic ! | |
271 | key_mask &= key_rpt; // read key(s) | |
272 | key_rpt ^= key_mask; // clear key(s) | |
273 | __enable_irq(); | |
274 | return key_mask; | |
275 | } | |
6b81b39f | 276 | */ |
e64eba00 L |
277 | |
278 | static uint16_t get_key_short(uint16_t key_mask) { | |
279 | __disable_irq(); | |
280 | // read key state and key press atomic ! | |
281 | return get_key_press(key_state & key_mask); | |
282 | } | |
283 | ||
284 | /* | |
285 | static uint16_t get_key_long(uint16_t key_mask) { | |
286 | return get_key_press(get_key_rpt(key_mask)); | |
287 | } | |
288 | */ | |
289 | ||
290 | static void key_timerproc() { | |
291 | static uint16_t key_in_last, rpt; | |
292 | uint16_t key_in, c; | |
293 | ||
294 | key_in = KEY_PORT; | |
295 | ||
296 | c = key_in_last & key_in & ~key_state; | |
297 | ||
298 | // key_state = key_state & key_in_last | (key_state | key_in_last) & key_in; | |
299 | // key_state = key_state & key_in | (key_state | key_in) & key_in_last; | |
300 | ||
301 | key_state = c | ((key_in_last | key_in) & key_state); | |
302 | ||
303 | // key_state = (key_state&key_in_last) | (key_state&key_in) | (key_in_last&key_in); | |
304 | ||
305 | key_press |= c; | |
306 | ||
307 | key_in_last = key_in; | |
308 | ||
309 | ||
310 | if ((key_state & REPEAT_MASK) == 0) // check repeat function | |
311 | rpt = REPEAT_START; | |
312 | if (--rpt == 0) { | |
313 | rpt = REPEAT_NEXT; // repeat delay | |
314 | key_rpt |= key_state & REPEAT_MASK; | |
315 | } | |
316 | ||
e64eba00 L |
317 | } |
318 | ||
319 | /*--------------------------------------------------------------------------*/ | |
320 | ||
321 | void sys_tick_handler(void) | |
322 | { | |
0c5890bb L |
323 | static int_fast8_t tick_10ms = 0; |
324 | static int_fast16_t count_ms = 0; | |
e64eba00 | 325 | |
0c5890bb | 326 | int_fast8_t i; |
e64eba00 L |
327 | |
328 | ++tick_10ms; | |
329 | if (tick_10ms == 10) | |
330 | { | |
331 | Stat |= S_10MS_TO; | |
332 | ||
333 | tick_10ms = 0; | |
334 | ||
335 | i = led_timer[0]; | |
336 | if (i) | |
337 | led_timer[0] = i - 1; | |
338 | i = led_timer[1]; | |
339 | if (i) | |
340 | led_timer[1] = i - 1; | |
341 | ||
342 | key_timerproc(); | |
343 | ||
344 | /* Drive timer procedure of low level disk I/O module */ | |
345 | //disk_timerproc(); | |
346 | } | |
347 | ||
348 | count_ms++; | |
349 | if (count_ms == 1000) { | |
350 | count_ms = 0; | |
351 | ||
0d318092 L |
352 | i = timeout_1s; |
353 | if (i) | |
354 | timeout_1s = i - 1; | |
e64eba00 L |
355 | } |
356 | } | |
357 | ||
358 | void rtc_isr(void) | |
359 | { | |
360 | /* The interrupt flag isn't cleared by hardware, we have to do it. */ | |
361 | rtc_clear_flag(RTC_SEC); | |
362 | ||
363 | } | |
364 | ||
365 | /*--------------------------------------------------------------------------*/ | |
366 | ||
367 | void tim3_set(int mode) | |
368 | { | |
369 | uint16_t cc_mode; | |
370 | ||
371 | cc_mode = TIM_CCMR2_CC4S_OUT; | |
372 | ||
0d318092 | 373 | TIM3_CR1 = TIM_CR1_CMS_EDGE | TIM_CR1_DIR_UP /*| TIM_CR1_OPM */ ; |
e64eba00 L |
374 | |
375 | if (mode < 0) | |
376 | cc_mode |= TIM_CCMR2_OC4M_FORCE_LOW; | |
377 | else if (mode == 0) | |
378 | cc_mode |= TIM_CCMR2_OC4M_FORCE_HIGH; | |
379 | else { | |
380 | TIM3_ARR = mode; | |
0d318092 | 381 | TIM3_CCR4 = mode/2; |
e64eba00 L |
382 | cc_mode |= TIM_CCMR2_OC4M_PWM2; |
383 | } | |
384 | ||
385 | TIM3_CCMR2 = cc_mode; | |
386 | ||
387 | if (mode > 0) | |
388 | TIM3_CR1 |= TIM_CR1_CEN; | |
389 | } | |
390 | ||
391 | /*--------------------------------------------------------------------------*/ | |
392 | ||
0c5890bb | 393 | static uint32_t z80_sram_cmp(uint32_t addr, uint32_t length, uint8_t wval, int inc) |
e64eba00 L |
394 | { |
395 | uint8_t rval; | |
0c5890bb | 396 | int_fast8_t errors = 0; |
e64eba00 | 397 | |
64045ba0 | 398 | DBG_P(1, "SRAM: Check 0x%.5lX byte... ", length); |
e64eba00 L |
399 | while (length--) { |
400 | if ((rval = z80_read(addr)) != wval) { | |
401 | if (errors == 0) { | |
402 | printf("\nSRAM: Address W R\n" \ | |
403 | " -------------\n"); | |
404 | // 12345 00 11 | |
405 | } | |
406 | printf(" %.5lx %.2x %.2x\n", addr, wval, rval); | |
407 | ||
408 | if (++errors > 16 ) | |
409 | break; | |
410 | } | |
411 | addr++; | |
412 | wval += inc; | |
413 | } | |
6b81b39f | 414 | DBG_P(1, "Done.\n"); |
e64eba00 L |
415 | |
416 | return addr; | |
417 | } | |
418 | ||
419 | #if 0 | |
420 | static void z80_sram_fill(uint32_t addr, int length, uint8_t startval, int inc) | |
421 | { | |
422 | printf("SRAM: Write %#.5x byte... ", length); //fflush(stdout); | |
423 | while (length--) { | |
424 | z80_write(addr, startval); | |
425 | ++addr; | |
426 | startval += inc; | |
427 | } | |
428 | printf("Done.\n"); | |
429 | } | |
430 | ||
431 | ||
432 | void z80_sram_fill_string(uint32_t addr, int length, const char *text) | |
433 | { | |
434 | char c; | |
435 | const char *p = text; | |
436 | ||
437 | while (length--) { | |
438 | z80_write(addr++, c = *p++); | |
439 | if (c == 0) | |
440 | p = text; | |
441 | } | |
442 | } | |
443 | ||
444 | ||
445 | uint32_t z80_sram_cmp_string(uint32_t addr, int length, const char *text) | |
446 | { | |
447 | char c; | |
448 | const char *p = text; | |
449 | ||
450 | while (length--) { | |
451 | c = *p++; | |
452 | if (z80_read(addr) != c) | |
453 | break; | |
454 | ++addr; | |
455 | if (c == 0) | |
456 | p = text; | |
457 | } | |
458 | return addr; | |
459 | } | |
460 | ||
461 | const char * const qbfox = "Zhe quick brown fox jumps over the lazy dog!"; | |
462 | const char * const qbcat = "Zhe quick brown fox jumps over the lazy cat!"; | |
463 | ||
464 | #endif | |
465 | ||
64045ba0 L |
466 | /*--------------------------------------------------------------------------*/ |
467 | ||
e64eba00 L |
468 | uint8_t z80_get_byte(uint32_t adr) |
469 | { | |
470 | uint8_t data; | |
471 | ||
0d318092 | 472 | z80_request_bus(); |
e64eba00 L |
473 | data = z80_read(adr), |
474 | z80_release_bus(); | |
475 | ||
476 | return data; | |
477 | } | |
478 | ||
479 | ||
480 | /*--------------------------------------------------------------------------*/ | |
481 | ||
482 | static void do_10ms(void) | |
483 | { | |
0d318092 | 484 | for (uint_fast8_t i = 0; i < 2; i++) { |
e64eba00 L |
485 | switch (led_stat[i].mode) { |
486 | case PULSE: | |
487 | if (led_timer[i] == 0) { | |
488 | led_off(i); | |
489 | led_stat[i].mode = NOTHING; | |
490 | } | |
491 | break; | |
492 | case BLINK1: | |
493 | case BLINK2: | |
494 | if (led_timer[i] == 0) { | |
495 | if (led_is_on(i)) | |
496 | led_timer[i] = led_stat[i].offtime; | |
497 | else | |
498 | led_timer[i] = led_stat[i].ontime; | |
499 | led_toggle(i); | |
500 | } | |
501 | break; | |
502 | default: | |
503 | break; | |
504 | } | |
505 | } | |
506 | } | |
507 | ||
d9c2b1b6 L |
508 | struct msg_item { |
509 | uint8_t fct; | |
510 | uint8_t sub_min, sub_max; | |
511 | void (*func)(uint8_t, int, uint8_t *); | |
512 | }; | |
513 | ||
64045ba0 | 514 | static |
d9c2b1b6 | 515 | uint32_t msg_to_addr(uint8_t *msg) |
6b81b39f | 516 | { |
0c5890bb | 517 | uint32_t addr = msg[0] | (msg[1] << 8) | ((uint32_t)msg[2] << 16); |
d9c2b1b6 L |
518 | |
519 | return addr; | |
520 | ||
6b81b39f L |
521 | } |
522 | ||
64045ba0 | 523 | static |
d9c2b1b6 | 524 | void do_msg_ini_msgfifo(uint8_t subf, int len, uint8_t * msg) |
6b81b39f | 525 | { |
d9c2b1b6 L |
526 | (void)subf; (void)len; |
527 | ||
528 | z80_init_msg_fifo(msg_to_addr(msg)); | |
529 | } | |
530 | ||
531 | ||
64045ba0 | 532 | static |
d9c2b1b6 L |
533 | void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg) |
534 | { | |
535 | (void)len; | |
536 | ||
537 | z80_memfifo_init(subf - 1, msg_to_addr(msg)); | |
6b81b39f L |
538 | } |
539 | ||
d9c2b1b6 | 540 | |
64045ba0 | 541 | static |
d9c2b1b6 L |
542 | void do_msg_char_out(uint8_t subf, int len, uint8_t * msg) |
543 | { | |
544 | (void)subf; | |
545 | ||
546 | while (len--) | |
547 | putchar(*msg++); | |
548 | } | |
549 | ||
550 | ||
64045ba0 | 551 | static |
d9c2b1b6 L |
552 | const struct msg_item z80_messages[] = |
553 | { | |
0c5890bb L |
554 | { 0, /* fct nr. */ |
555 | 0, 0, /* sub fct nr. from, to */ | |
d9c2b1b6 L |
556 | &do_msg_ini_msgfifo}, |
557 | { 0, | |
558 | 1, 2, | |
559 | &do_msg_ini_memfifo}, | |
560 | { 1, | |
561 | 1, 1, | |
562 | &do_msg_char_out}, | |
563 | { 0xff, /* end mark */ | |
564 | 0, 0, | |
565 | 0}, | |
566 | ||
567 | }; | |
568 | ||
569 | ||
570 | ||
571 | ||
64045ba0 | 572 | static |
6b81b39f L |
573 | void do_message(int len, uint8_t *msg) |
574 | { | |
d9c2b1b6 | 575 | uint8_t fct, sub_fct; |
0c5890bb | 576 | int_fast8_t i = 0; |
6b81b39f | 577 | |
d9c2b1b6 L |
578 | if (len >= 2) { |
579 | fct = *msg++; | |
580 | sub_fct = *msg++; | |
581 | len -= 2; | |
582 | ||
583 | while (fct != z80_messages[i].fct) | |
584 | ++i; | |
585 | ||
586 | if (z80_messages[i].fct == 0xff) { | |
587 | DBG_P(1, "do_message: Unknown function: %i, %i\n", | |
588 | fct, sub_fct); | |
589 | return; /* TODO: unknown message # */ | |
590 | } | |
591 | ||
592 | while (fct == z80_messages[i].fct) { | |
593 | if (sub_fct >= z80_messages[i].sub_min && sub_fct <= z80_messages[i].sub_max ) | |
594 | break; | |
595 | ++i; | |
6b81b39f | 596 | } |
d9c2b1b6 L |
597 | |
598 | if (z80_messages[i].fct != fct) { | |
599 | DBG_P(1, "do_message: Unknown sub function: %i, %i\n", | |
600 | fct, sub_fct); | |
601 | return; /* TODO: unknown message sub# */ | |
602 | } | |
603 | ||
604 | (z80_messages[i].func)(sub_fct, len, msg); | |
605 | ||
606 | ||
6b81b39f | 607 | } else { |
d9c2b1b6 L |
608 | /* TODO: error */ |
609 | DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len); | |
6b81b39f L |
610 | } |
611 | } | |
612 | ||
613 | ||
6b81b39f | 614 | |
d9c2b1b6 L |
615 | #define CTRBUF_LEN 256 |
616 | ||
64045ba0 | 617 | static |
d9c2b1b6 | 618 | void check_msg_fifo(void) |
0d318092 | 619 | { |
6b81b39f | 620 | int ch; |
0c5890bb | 621 | static int_fast8_t state; |
6b81b39f L |
622 | static int msglen,idx; |
623 | static uint8_t buffer[CTRBUF_LEN]; | |
624 | ||
625 | while (state != 3 && (ch = z80_msg_fifo_getc()) >= 0) { | |
626 | switch (state) { | |
627 | case 0: /* wait for start of message */ | |
628 | if (ch == 0x81) { | |
629 | msglen = 0; | |
630 | idx = 0; | |
631 | state = 1; | |
632 | } | |
633 | break; | |
634 | case 1: /* get msg len */ | |
635 | if (ch > 0 && ch <= CTRBUF_LEN) { | |
636 | msglen = ch; | |
637 | state = 2; | |
638 | } else | |
639 | state = 0; | |
640 | break; | |
641 | case 2: /* get message */ | |
642 | buffer[idx++] = ch; | |
643 | if (idx == msglen) | |
644 | state = 3; | |
645 | break; | |
0d318092 L |
646 | } |
647 | } | |
6b81b39f L |
648 | |
649 | if (state == 3) { | |
650 | do_message(msglen, buffer); | |
651 | state = 0; | |
652 | } | |
0d318092 L |
653 | } |
654 | ||
6b81b39f L |
655 | |
656 | void z80_load_mem(void) | |
657 | { | |
6b81b39f L |
658 | unsigned sec = 0; |
659 | uint32_t sec_base = hdrom_start; | |
660 | ||
0c5890bb L |
661 | DBG_P(1, "Loading z80 memory... \n"); |
662 | ||
6b81b39f L |
663 | while (sec < hdrom_sections) { |
664 | DBG_P(2, " From: 0x%.5lX to: 0x%.5lX (%5li bytes)\n", | |
665 | hdrom_address[sec], | |
666 | hdrom_address[sec]+hdrom_length_of_sections[sec] - 1, | |
667 | hdrom_length_of_sections[sec]); | |
668 | ||
669 | z80_write_block((unsigned char *) &hdrom[sec_base], /* src */ | |
670 | hdrom_address[sec], /* dest */ | |
671 | hdrom_length_of_sections[sec]); /* len */ | |
672 | sec_base+=hdrom_length_of_sections[sec]; | |
673 | sec++; | |
674 | } | |
675 | } | |
e64eba00 L |
676 | /*--------------------------------------------------------------------------*/ |
677 | ||
678 | int main(void) | |
679 | { | |
0c5890bb | 680 | int_fast8_t state = 0; |
6b81b39f | 681 | int ch; |
e64eba00 L |
682 | |
683 | clock_setup(); | |
684 | gpio_setup(); | |
685 | tim3_setup(); | |
686 | setvbuf(stdout, NULL, _IONBF, 0); | |
6b81b39f | 687 | serial_setup(); |
0d318092 | 688 | printf("\n(STM32F100+HD64180)_stamp Tester\n"); |
e64eba00 | 689 | |
6b81b39f L |
690 | DBG_P(1, "z80_setup_bus... "); |
691 | z80_setup_msg_fifo(); | |
e64eba00 | 692 | z80_setup_bus(); |
6b81b39f | 693 | DBG_P(1, "done.\n"); |
e64eba00 L |
694 | |
695 | /* | |
696 | * If the RTC is pre-configured just allow access, don't reconfigure. | |
697 | * Otherwise enable it with the LSE as clock source and 0x7fff as | |
698 | * prescale value. | |
699 | */ | |
700 | rtc_auto_awake(LSE, 0x7fff); | |
701 | ||
702 | systick_setup(); | |
e64eba00 | 703 | |
6b81b39f | 704 | DBG_P(1, "Get bus... "); |
e64eba00 L |
705 | z80_busreq(LOW); |
706 | z80_reset(HIGH); | |
0d318092 | 707 | z80_request_bus(); |
6b81b39f | 708 | DBG_P(1, "got it!\n"); |
e64eba00 L |
709 | |
710 | z80_memset(0, 0x76, 0x80000); | |
711 | //z80_sram_fill(0, 512 * 1024, 0x76, 0); | |
0c5890bb | 712 | z80_sram_cmp(0, (uint32_t)512 * 1024, 0x76, 0); |
e64eba00 | 713 | |
6b81b39f | 714 | z80_load_mem(); |
e64eba00 | 715 | z80_reset(LOW); |
6b81b39f | 716 | DBG_P(1, "Bus released!\n"); |
e64eba00 L |
717 | z80_release_bus(); |
718 | z80_reset(HIGH); | |
6b81b39f | 719 | DBG_P(1, "Reset released!\n"); |
e64eba00 | 720 | |
e64eba00 L |
721 | |
722 | ledset(0, BLINK1, 50); | |
723 | ||
724 | while (1) { | |
6b81b39f | 725 | |
e64eba00 L |
726 | if (Stat & S_10MS_TO) { |
727 | Stat &= ~S_10MS_TO; | |
728 | do_10ms(); | |
729 | } | |
730 | ||
0d318092 | 731 | if (get_key_short(KEY0)) { |
e64eba00 | 732 | z80_reset_pulse(); |
0d318092 | 733 | } |
e64eba00 | 734 | |
6b81b39f L |
735 | if ((ch = serial_getc()) >= 0) { |
736 | switch (state) { | |
e64eba00 | 737 | case 0: |
6b81b39f L |
738 | if (ch == ESCCHAR) { |
739 | state = 1; | |
740 | /* TODO: Timer starten */ | |
741 | } else | |
742 | z80_memfifo_putc(fifo_out, ch); | |
e64eba00 | 743 | break; |
6b81b39f L |
744 | case 1: |
745 | switch (ch) { | |
e64eba00 | 746 | |
6b81b39f | 747 | case 'h': /* test: green led on */ |
e64eba00 L |
748 | tim3_set(-1); |
749 | break; | |
6b81b39f | 750 | case 'l': /* test: green led off */ |
e64eba00 L |
751 | tim3_set(0); |
752 | break; | |
6b81b39f L |
753 | case 'p': /* test: pulse on led pin */ |
754 | tim3_set(24000000 / 1000000 * 5); /* 5 us */ | |
755 | break; | |
756 | case 'r': | |
757 | z80_reset_pulse(); | |
e64eba00 | 758 | break; |
e64eba00 | 759 | |
6b81b39f L |
760 | case ESCCHAR: |
761 | default: | |
762 | z80_memfifo_putc(fifo_out, ch); | |
763 | } | |
764 | state = 0; | |
765 | break; | |
e64eba00 | 766 | } |
e64eba00 | 767 | } |
0d318092 | 768 | |
6b81b39f | 769 | check_msg_fifo(); |
e64eba00 L |
770 | } |
771 | ||
772 | return 0; | |
773 | } |