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Interrupt driven Serial I/O, msg-fifo, do_msg..., debug msgs
[z180-stamp.git] / stm32 / z180-stamp-stm32.c
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1/*
2 */
3
e64eba00 4#include <stdio.h>
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5
6#include <libopencmsis/core_cm3.h>
7#include <libopencm3/cm3/nvic.h>
8#include <libopencm3/cm3/systick.h>
9#include <libopencm3/stm32/rtc.h>
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10#include <libopencm3/stm32/rcc.h>
11#include <libopencm3/stm32/gpio.h>
12#include <libopencm3/stm32/timer.h>
13
14#define ODR 0x0c
15#define IDR 0x08
16
17
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18#include "debug.h"
19#include "serial.h"
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20#include "z80-if.h"
21#include "hdrom.h"
22
e64eba00 23
6b81b39f 24#define ESCCHAR ('^'-0x40)
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25
26#define S_10MS_TO (1<<0)
27
28/*
29 * LED Connections
30 */
31
32#define LED_PORT GPIOC
33#define LED_BLUE_PIN GPIO8
34#define BLUE 8
35#define LED_GREEN_PIN GPIO9
36#define GREEN 9
37
38
39#define LED_BLUE_ON() BBIO_PERIPH(LED_PORT+ODR, BLUE) = 1
40#define LED_BLUE_OFF() BBIO_PERIPH(LED_PORT+ODR, BLUE) = 0
41#define LED_BLUE_TOGGLE() BBIO_PERIPH(LED_PORT+ODR, BLUE) = !BBIO_PERIPH(LED_PORT+ODR, BLUE)
42
43#define LED_GREEN_ON() BBIO_PERIPH(LED_PORT+ODR, GREEN) = 1
44#define LED_GREEN_OFF() BBIO_PERIPH(LED_PORT+ODR, GREEN) = 0
45#define LED_GREEN_TOGGLE() BBIO_PERIPH(LED_PORT+ODR, GREEN) = !BBIO_PERIPH(LED_PORT+ODR, GREEN)
46
47
48/*
49 * Button connections
50 */
51
52//BBIO_PERIPH(GPIOA+IDR, 0);
53
54#define KEY_PORT GPIOA_IDR
55#define KEY0 GPIO0
56//#define KEY1 GPIO1
57//#define KEY2 GPIO2
58
59#define REPEAT_MASK KEY0 // repeat: key0
60#define REPEAT_START 100 // after 1s
61#define REPEAT_NEXT 20 // every 200ms
62
63
64typedef enum {
65 NOTHING, PULSE, BLINK1, BLINK2
66} LED_MODE;
67
68typedef struct {
69 uint8_t mode;
70 uint8_t ontime, offtime;
71} led_stat_t;
72
73volatile uint8_t led_timer[2];
74led_stat_t led_stat[2];
75
76volatile int timeout_1s;
77volatile uint32_t Stat;
78
79
80/*--------------------------------------------------------------------------*/
81
82
83static void clock_setup(void)
84{
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85 //rcc_clock_setup_in_hse_8mhz_out_24mhz();
86 rcc_clock_setup_in_hsi_out_24mhz();
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87
88 /* Enable clocks for:
89 GPIO port A (for GPIO_USART1_TX and Button)
90 GPIO port C (LEDs)
91 USART1
92 TIM16 (RST-Pin)
0d318092 93 TIM1 (IOCS1)
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94 */
95 rcc_peripheral_enable_clock(&RCC_APB2ENR,
96 RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN
97 | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN
98 | RCC_APB2ENR_USART1EN | RCC_APB2ENR_AFIOEN
99 | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM16EN);
100 /* Enable clocks for:
101 TIM3
102 */
103 rcc_peripheral_enable_clock(&RCC_APB1ENR,
104 RCC_APB1ENR_TIM3EN);
105
106 /* Enable clocks for:
0d318092 107 DMA1
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108 */
109 rcc_peripheral_enable_clock(&RCC_AHBENR,
110 RCC_AHBENR_DMA1EN);
111}
112
113static void systick_setup(void)
114{
115 /* SysTick interrupt every N clock pulses: set reload to N-1 */
116 STK_RVR = 24000000/1000 - 1;
117
118 /* Set source to core clock, enable int and start counting. */
119 STK_CSR = STK_CSR_CLKSOURCE_AHB | STK_CSR_TICKINT | STK_CSR_ENABLE;
120}
121
122#if 0
123static void nvic_setup(void)
124{
125// nvic_enable_irq(NVIC_RTC_IRQ);
126// nvic_set_priority(NVIC_RTC_IRQ, 1);
127}
128#endif
129
130static void tim3_setup(void)
131{
132 TIM3_CR1 = TIM_CR1_CMS_EDGE | TIM_CR1_DIR_UP;
133
134 TIM3_CCMR2 = 0
135 | TIM_CCMR2_OC4M_FORCE_LOW
136 /* | TIM_CCMR2_OC4M_FORCE_HIGH */
137 /* | TIM_CCMR2_OC4M_PWM2 */
138
139 /* | TIM_CCMR2_OC4PE */
140 /* | TIM_CCMR2_OC4FE */
141 | TIM_CCMR2_CC4S_OUT;
142
143 TIM3_CCER = TIM_CCER_CC4E
144 | TIM_CCER_CC4P;
145
146 TIM3_ARR = 48; /* default */
147 TIM3_CCR4 = 1; /* */
148}
149
150static void gpio_setup(void)
151{
152
153 /* Disable JTAG-DP, but leave SW-DP Enabled. (free PA15, PB3, PB4)
154 Remap SPI1 to PB3, PB4, PB5 and PA15.
155 Remap TIM3 (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
0d318092 156 Port D0/Port D1 mapping on OSC_IN/OSC_OUT
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157 */
158 gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON,
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159 AFIO_MAPR_SPI1_REMAP
160 | AFIO_MAPR_TIM3_REMAP_FULL_REMAP
161 | AFIO_MAPR_PD01_REMAP);
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162
163 /* LEDs and User Button. */
164 gpio_set_mode(LED_PORT, GPIO_MODE_OUTPUT_2_MHZ,
165 GPIO_CNF_OUTPUT_PUSHPULL, LED_BLUE_PIN);
166 gpio_set_mode(LED_PORT, GPIO_MODE_OUTPUT_10_MHZ,
167 GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, LED_GREEN_PIN);
168 gpio_set_mode(GPIOA, GPIO_MODE_INPUT,
169 GPIO_CNF_INPUT_FLOAT, GPIO0);
170}
171
172
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173/*--------------------------------------------------------------------------*/
174
175void delay_systicks(int ticks)
176{
177 int start, stop, now;
178
179 start = STK_CVR;
180 stop = start - ticks;
181 if (stop < 0) {
182 stop += STK_RVR;
183 do {
184 now = STK_CVR;
185 } while ((now > stop) || (now <= start));
186 } else {
187 do {
188 now = STK_CVR;
189 } while ((now > stop) && (now <= start));
190 }
191}
192
193
194/*--------------------------------------------------------------------------*/
195
196static void led_toggle(uint8_t lednr) {
197 if (lednr == 0)
198 LED_BLUE_TOGGLE();
199 else if (lednr == 1)
200 LED_GREEN_TOGGLE();
201}
202
203static void led_on(uint8_t lednr) {
204 if (lednr == 0)
205 LED_BLUE_ON();
206 else if (lednr == 1)
207 LED_GREEN_ON();
208}
209
210static void led_off(uint8_t lednr) {
211 if (lednr == 0)
212 LED_BLUE_OFF();
213 else if (lednr == 1)
214 LED_GREEN_OFF();
215}
216
217static uint8_t led_is_on(uint8_t lednr) {
218 if (lednr == 0)
219 return BBIO_PERIPH(LED_PORT+ODR, BLUE);
220 else if (lednr == 1)
221 return BBIO_PERIPH(LED_PORT+ODR, GREEN);
222 else
223 return 0;
224}
225
226static void ledset(uint8_t lednr, uint8_t what, uint8_t len) {
227
228 led_stat[lednr].mode = what;
229 switch (what) {
230 case PULSE:
231 led_stat[lednr].ontime = len;
232 led_stat[lednr].offtime = 0;
233 led_timer[lednr] = len;
234 led_on(lednr);
235 break;
236 case BLINK1:
237 case BLINK2:
238 if (what == BLINK1)
239 led_stat[lednr].offtime = 100 - len;
240 else
241 led_stat[lednr].offtime = 200 - len;
242 led_stat[lednr].ontime = len;
243 led_timer[lednr] = len;
244 led_on(lednr);
245 break;
246 default:
247 break;
248 }
249}
250
251/*--------------------------------------------------------------------------*/
252
253static volatile uint16_t key_state,
254 key_press, // key press detect
255 key_rpt; // key long press and repeat
256
257
258static uint16_t get_key_press(uint16_t key_mask) {
259 __disable_irq();
260 // read and clear atomic !
261 key_mask &= key_press; // read key(s)
262 key_press ^= key_mask; // clear key(s)
263 __enable_irq();
264 return key_mask;
265}
266
6b81b39f 267/*
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268static uint16_t get_key_rpt(uint16_t key_mask) {
269 __disable_irq();
270 // read and clear atomic !
271 key_mask &= key_rpt; // read key(s)
272 key_rpt ^= key_mask; // clear key(s)
273 __enable_irq();
274 return key_mask;
275}
6b81b39f 276*/
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277
278static uint16_t get_key_short(uint16_t key_mask) {
279 __disable_irq();
280 // read key state and key press atomic !
281 return get_key_press(key_state & key_mask);
282}
283
284/*
285static uint16_t get_key_long(uint16_t key_mask) {
286 return get_key_press(get_key_rpt(key_mask));
287}
288*/
289
290static void key_timerproc() {
291 static uint16_t key_in_last, rpt;
292 uint16_t key_in, c;
293
294 key_in = KEY_PORT;
295
296 c = key_in_last & key_in & ~key_state;
297
298// key_state = key_state & key_in_last | (key_state | key_in_last) & key_in;
299// key_state = key_state & key_in | (key_state | key_in) & key_in_last;
300
301 key_state = c | ((key_in_last | key_in) & key_state);
302
303// key_state = (key_state&key_in_last) | (key_state&key_in) | (key_in_last&key_in);
304
305 key_press |= c;
306
307 key_in_last = key_in;
308
309
310 if ((key_state & REPEAT_MASK) == 0) // check repeat function
311 rpt = REPEAT_START;
312 if (--rpt == 0) {
313 rpt = REPEAT_NEXT; // repeat delay
314 key_rpt |= key_state & REPEAT_MASK;
315 }
316
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317}
318
319/*--------------------------------------------------------------------------*/
320
321void sys_tick_handler(void)
322{
323 static int tick_10ms = 0;
324 static int count_ms = 0;
325
326 int i;
327
328 ++tick_10ms;
329 if (tick_10ms == 10)
330 {
331 Stat |= S_10MS_TO;
332
333 tick_10ms = 0;
334
335 i = led_timer[0];
336 if (i)
337 led_timer[0] = i - 1;
338 i = led_timer[1];
339 if (i)
340 led_timer[1] = i - 1;
341
342 key_timerproc();
343
344 /* Drive timer procedure of low level disk I/O module */
345 //disk_timerproc();
346 }
347
348 count_ms++;
349 if (count_ms == 1000) {
350 count_ms = 0;
351
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352 i = timeout_1s;
353 if (i)
354 timeout_1s = i - 1;
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355 }
356}
357
358void rtc_isr(void)
359{
360 /* The interrupt flag isn't cleared by hardware, we have to do it. */
361 rtc_clear_flag(RTC_SEC);
362
363}
364
365/*--------------------------------------------------------------------------*/
366
367void tim3_set(int mode)
368{
369 uint16_t cc_mode;
370
371 cc_mode = TIM_CCMR2_CC4S_OUT;
372
0d318092 373 TIM3_CR1 = TIM_CR1_CMS_EDGE | TIM_CR1_DIR_UP /*| TIM_CR1_OPM */ ;
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374
375 if (mode < 0)
376 cc_mode |= TIM_CCMR2_OC4M_FORCE_LOW;
377 else if (mode == 0)
378 cc_mode |= TIM_CCMR2_OC4M_FORCE_HIGH;
379 else {
380 TIM3_ARR = mode;
0d318092 381 TIM3_CCR4 = mode/2;
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382 cc_mode |= TIM_CCMR2_OC4M_PWM2;
383 }
384
385 TIM3_CCMR2 = cc_mode;
386
387 if (mode > 0)
388 TIM3_CR1 |= TIM_CR1_CEN;
389}
390
391/*--------------------------------------------------------------------------*/
392
393static uint32_t z80_sram_cmp(uint32_t addr, int length, uint8_t wval, int inc)
394{
395 uint8_t rval;
396 int errors = 0;
397
6b81b39f 398 DBG_P(1, "SRAM: Check %#.5x byte... ", length);
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399 while (length--) {
400 if ((rval = z80_read(addr)) != wval) {
401 if (errors == 0) {
402 printf("\nSRAM: Address W R\n" \
403 " -------------\n");
404// 12345 00 11
405 }
406 printf(" %.5lx %.2x %.2x\n", addr, wval, rval);
407
408 if (++errors > 16 )
409 break;
410 }
411 addr++;
412 wval += inc;
413 }
6b81b39f 414 DBG_P(1, "Done.\n");
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415
416 return addr;
417}
418
419#if 0
420static void z80_sram_fill(uint32_t addr, int length, uint8_t startval, int inc)
421{
422 printf("SRAM: Write %#.5x byte... ", length); //fflush(stdout);
423 while (length--) {
424 z80_write(addr, startval);
425 ++addr;
426 startval += inc;
427 }
428 printf("Done.\n");
429}
430
431
432void z80_sram_fill_string(uint32_t addr, int length, const char *text)
433{
434 char c;
435 const char *p = text;
436
437 while (length--) {
438 z80_write(addr++, c = *p++);
439 if (c == 0)
440 p = text;
441 }
442}
443
444
445uint32_t z80_sram_cmp_string(uint32_t addr, int length, const char *text)
446{
447 char c;
448 const char *p = text;
449
450 while (length--) {
451 c = *p++;
452 if (z80_read(addr) != c)
453 break;
454 ++addr;
455 if (c == 0)
456 p = text;
457 }
458 return addr;
459}
460
461const char * const qbfox = "Zhe quick brown fox jumps over the lazy dog!";
462const char * const qbcat = "Zhe quick brown fox jumps over the lazy cat!";
463
464#endif
465
466uint8_t z80_get_byte(uint32_t adr)
467{
468 uint8_t data;
469
0d318092 470 z80_request_bus();
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471 data = z80_read(adr),
472 z80_release_bus();
473
474 return data;
475}
476
477
478/*--------------------------------------------------------------------------*/
479
480static void do_10ms(void)
481{
0d318092 482 for (uint_fast8_t i = 0; i < 2; i++) {
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483 switch (led_stat[i].mode) {
484 case PULSE:
485 if (led_timer[i] == 0) {
486 led_off(i);
487 led_stat[i].mode = NOTHING;
488 }
489 break;
490 case BLINK1:
491 case BLINK2:
492 if (led_timer[i] == 0) {
493 if (led_is_on(i))
494 led_timer[i] = led_stat[i].offtime;
495 else
496 led_timer[i] = led_stat[i].ontime;
497 led_toggle(i);
498 }
499 break;
500 default:
501 break;
502 }
503 }
504}
505
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506static
507void do_msg_init(int len, uint8_t* msg)
508{
509 uint8_t sub_fct;
510
511 if (len > 0) {
512 len--;
513 switch (sub_fct = *msg++) {
514 case 0:
515 case 1:
516 case 2:
517 if (len == 3) {
518 uint32_t fifoadr = 0;
519 while (len--)
520 fifoadr = (fifoadr << 8) + msg[len];
521 if (sub_fct == 0)
522 z80_init_msg_fifo(fifoadr);
523 else
524 z80_memfifo_init(sub_fct - 1, fifoadr);
525 } else {
526 /* garbage from z180 */
527 }
528 break;
529 default:
530 /* garbage from z180 */
531 break;
532 }
533 }
534}
535
536static
537void do_msg_char(int len, uint8_t* msg)
538{
539 uint8_t sub_fct;
540
541 if (len > 0) {
542 len--;
543 switch (sub_fct = *msg++) {
544 case 1: /* console output */
545 while (len--)
546 putchar(*msg++);
547 break;
548 }
549 }
550}
551
552static
553void do_message(int len, uint8_t *msg)
554{
555 uint8_t sub_fct;
556
557 if (len > 0) {
558 len--;
559 switch (*msg++) {
560 case 0: /* init functions */
561 do_msg_init(len, msg);
562 break;
563 case 1: /* character i/o functions */
564 do_msg_char(len, msg);
565 break;
566 default:
567 /* no more functions definded yet*/
568 break;
569 }
570 } else {
571 /* shoudn't happen */
572 }
573}
574
575
576#define CTRBUF_LEN 20
577
578static void check_msg_fifo(void)
0d318092 579{
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580 int ch;
581 static int state;
582 static int msglen,idx;
583 static uint8_t buffer[CTRBUF_LEN];
584
585 while (state != 3 && (ch = z80_msg_fifo_getc()) >= 0) {
586 switch (state) {
587 case 0: /* wait for start of message */
588 if (ch == 0x81) {
589 msglen = 0;
590 idx = 0;
591 state = 1;
592 }
593 break;
594 case 1: /* get msg len */
595 if (ch > 0 && ch <= CTRBUF_LEN) {
596 msglen = ch;
597 state = 2;
598 } else
599 state = 0;
600 break;
601 case 2: /* get message */
602 buffer[idx++] = ch;
603 if (idx == msglen)
604 state = 3;
605 break;
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606 }
607 }
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608
609 if (state == 3) {
610 do_message(msglen, buffer);
611 state = 0;
612 }
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613}
614
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615
616void z80_load_mem(void)
617{
618
619DBG_P(1, "Loading z80 memory... \n");
620
621 unsigned sec = 0;
622 uint32_t sec_base = hdrom_start;
623
624 while (sec < hdrom_sections) {
625 DBG_P(2, " From: 0x%.5lX to: 0x%.5lX (%5li bytes)\n",
626 hdrom_address[sec],
627 hdrom_address[sec]+hdrom_length_of_sections[sec] - 1,
628 hdrom_length_of_sections[sec]);
629
630 z80_write_block((unsigned char *) &hdrom[sec_base], /* src */
631 hdrom_address[sec], /* dest */
632 hdrom_length_of_sections[sec]); /* len */
633 sec_base+=hdrom_length_of_sections[sec];
634 sec++;
635 }
636}
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637/*--------------------------------------------------------------------------*/
638
639int main(void)
640{
641 //uint32_t led_state = LED_BLUE_PIN;
642 //uint32_t rc;
643 //uint8_t startval = 0;
644 //int count;
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645 int state = 0;
646 int ch;
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647
648 clock_setup();
649 gpio_setup();
650 tim3_setup();
651 setvbuf(stdout, NULL, _IONBF, 0);
6b81b39f 652 serial_setup();
0d318092 653 printf("\n(STM32F100+HD64180)_stamp Tester\n");
e64eba00 654
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655 DBG_P(1, "z80_setup_bus... ");
656 z80_setup_msg_fifo();
e64eba00 657 z80_setup_bus();
6b81b39f 658 DBG_P(1, "done.\n");
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659
660 /*
661 * If the RTC is pre-configured just allow access, don't reconfigure.
662 * Otherwise enable it with the LSE as clock source and 0x7fff as
663 * prescale value.
664 */
665 rtc_auto_awake(LSE, 0x7fff);
666
667 systick_setup();
e64eba00 668
6b81b39f 669 DBG_P(1, "Get bus... ");
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670 z80_busreq(LOW);
671 z80_reset(HIGH);
0d318092 672 z80_request_bus();
6b81b39f 673 DBG_P(1, "got it!\n");
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674
675 z80_memset(0, 0x76, 0x80000);
676 //z80_sram_fill(0, 512 * 1024, 0x76, 0);
677 z80_sram_cmp(0, 512 * 1024, 0x76, 0);
678
6b81b39f 679 z80_load_mem();
e64eba00 680 z80_reset(LOW);
6b81b39f 681 DBG_P(1, "Bus released!\n");
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682 z80_release_bus();
683 z80_reset(HIGH);
6b81b39f 684 DBG_P(1, "Reset released!\n");
e64eba00 685
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686
687 ledset(0, BLINK1, 50);
688
689 while (1) {
6b81b39f 690
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691 if (Stat & S_10MS_TO) {
692 Stat &= ~S_10MS_TO;
693 do_10ms();
694 }
695
0d318092 696 if (get_key_short(KEY0)) {
e64eba00 697 z80_reset_pulse();
0d318092 698 }
e64eba00 699
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700 if ((ch = serial_getc()) >= 0) {
701 switch (state) {
e64eba00 702 case 0:
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703 if (ch == ESCCHAR) {
704 state = 1;
705 /* TODO: Timer starten */
706 } else
707 z80_memfifo_putc(fifo_out, ch);
e64eba00 708 break;
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709 case 1:
710 switch (ch) {
e64eba00 711
6b81b39f 712 case 'h': /* test: green led on */
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713 tim3_set(-1);
714 break;
6b81b39f 715 case 'l': /* test: green led off */
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716 tim3_set(0);
717 break;
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718 case 'p': /* test: pulse on led pin */
719 tim3_set(24000000 / 1000000 * 5); /* 5 us */
720 break;
721 case 'r':
722 z80_reset_pulse();
e64eba00 723 break;
e64eba00 724
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725 case ESCCHAR:
726 default:
727 z80_memfifo_putc(fifo_out, ch);
728 }
729 state = 0;
730 break;
e64eba00 731 }
e64eba00 732 }
0d318092 733
6b81b39f 734 check_msg_fifo();
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735 }
736
737 return 0;
738}