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Commit | Line | Data |
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226d3221 L |
1 | .z80 ; for M80, ignored by SLR assembler\r |
2 | include z180reg.inc\r | |
3 | \r | |
4 | RUN_TPA equ 0\r | |
5 | \r | |
6 | UUNKNOWN equ 0 ;Unknown CPU\r | |
7 | U8080 equ 1 ;8080\r | |
8 | U8085 equ 2 ;8085\r | |
9 | UZ80 equ 3 ;Z80\r | |
10 | UX180 equ 4 ;HD64180 or higher\r | |
11 | UHD64180 equ 5 ;HD64180\r | |
12 | UZ80180 equ 6 ;Z80180\r | |
13 | UZ8S180 equ 7 ;Z8S180, Z8L180\r | |
14 | \r | |
15 | \r | |
16 | ;-------------------------------------------------------------------------------\r | |
17 | \r | |
18 | \r | |
19 | if RUN_TPA\r | |
20 | base equ 0100h\r | |
21 | else\r | |
22 | base equ 0\r | |
23 | endif\r | |
24 | \r | |
25 | \r | |
26 | aseg\r | |
27 | org base\r | |
28 | jp start\r | |
29 | \r | |
30 | done: db 0\r | |
31 | result: db 0\r | |
32 | \r | |
33 | ;-------------------------------------------------------------------------------\r | |
34 | ; Read internal register at address in L and IOBASE in H.\r | |
35 | ;\r | |
36 | \r | |
37 | reg_in:\r | |
38 | ld a,h\r | |
39 | add a,l\r | |
40 | ld c,a\r | |
41 | ld b,0\r | |
42 | in a,(c)\r | |
43 | ret\r | |
44 | \r | |
45 | ;-------------------------------------------------------------------------------\r | |
46 | ; Write internal register at address in L and IOBASE in H.\r | |
47 | ;\r | |
48 | \r | |
49 | reg_out:\r | |
50 | ld b,a\r | |
51 | ld a,h\r | |
52 | add a,l\r | |
53 | ld c,a\r | |
54 | ld a,b\r | |
55 | ld b,0\r | |
56 | out (c),a\r | |
57 | ret\r | |
58 | \r | |
59 | ;-------------------------------------------------------------------------------\r | |
60 | ; Check if register C exists. D holds mask of bit to test.\r | |
61 | ; return nz, if register exists\r | |
62 | \r | |
63 | chk_reg:\r | |
64 | call reg_in\r | |
65 | cp 0ffh\r | |
66 | ret nz ;\r | |
67 | \r | |
68 | ; check, if register is changeable\r | |
69 | \r | |
70 | xor d ; set bit(s) in register to 0\r | |
71 | call reg_out\r | |
72 | call reg_in ; get it back\r | |
73 | ex af,af'\r | |
74 | ld a,0ffh ; set to register original state\r | |
75 | call reg_out\r | |
76 | ex af,af'\r | |
77 | cpl\r | |
78 | and d\r | |
79 | ret\r | |
80 | \r | |
81 | ;-------------------------------------------------------------------------------\r | |
82 | ; Check CPU\r | |
83 | ;\r | |
84 | ;\r | |
85 | ; return:\r | |
86 | ; E = 0 Unknown\r | |
87 | ; E = 1 8080\r | |
88 | ; E = 2 8085\r | |
89 | ; E = 3 Z80\r | |
90 | ; E = 4 HD64180 or higher\r | |
91 | ; E = 5 HD64180\r | |
92 | ; E = 6 Z80180\r | |
93 | ; E = 7 Z8S180, Z8L180\r | |
94 | ;\r | |
95 | ;-------------------------------------------------------------------------------\r | |
96 | ; Registers only in Z180+, not in HD64180\r | |
97 | ; 3E OMCR\r | |
98 | ;\r | |
99 | ; Registers only in Z8S180/Z8L180\r | |
100 | ; 12 ASEXT0\r | |
101 | ; 13 ASEXT1\r | |
102 | ; 1A ASTC0L\r | |
103 | ; 1B ASTC0H\r | |
104 | ; 1C ASTC1L\r | |
105 | ; 1D ASTC1H\r | |
106 | ; 1E CMR\r | |
107 | ; 1F CCR\r | |
108 | ; 2D IAR1B\r | |
109 | ;\r | |
110 | ; Reserved registers\r | |
111 | ; 11\r | |
112 | ; 19\r | |
113 | ; 35\r | |
114 | ; 37\r | |
115 | ; 3B - 3D\r | |
116 | \r | |
117 | check:\r | |
118 | ld e,U8080 ; Init return val, assume 8080\r | |
119 | xor a\r | |
120 | dec a ; 00 --> 0FFH 8080/8085: even parity; Z80+: No overflow\r | |
121 | jp po,chk_z80 ; Z80+ if P/V flag reset\r | |
122 | \r | |
123 | ; The 8085 logical AND instructions always set the auxiliary flag ON.\r | |
124 | ; The 8080 logical AND instructions set the flag to reflect the\r | |
125 | ; logical OR of bit 3 of the values involved in the AND operation.\r | |
126 | ; (8080/8085 ASSEMBLY LANGUAGE PROGRAMMING MANUAL, 1977, 1978)\r | |
127 | \r | |
128 | xor a\r | |
129 | and a ; 8085 sets, 8080 resets half carry.\r | |
130 | daa ; A=06 (8085) or A=00 (8080)\r | |
131 | ret z\r | |
132 | inc e\r | |
133 | ret\r | |
134 | \r | |
135 | chk_z80:\r | |
136 | ld e,UZ80 ; Assume Z80\r | |
137 | daa ; Z80: 099H, x180+: 0F9H\r | |
138 | cp 99h ; Result on 180 type cpus is F9 here. Thanks Hitachi\r | |
139 | ret z\r | |
140 | inc e ; x180\r | |
141 | \r | |
142 | ; At least Hitachi HD64180\r | |
143 | ; Test differences in certain internal registers\r | |
144 | ; to determine the 180 variant.\r | |
145 | ; First, search the internal register bank.\r | |
146 | \r | |
147 | ld h,00H ; I/O Base\r | |
148 | find_base_loop:\r | |
149 | ld l,icr\r | |
150 | call reg_in\r | |
151 | and 11011111b ; mask I/O Stop bit\r | |
152 | xor h\r | |
153 | cp 01FH\r | |
154 | jr nz,nxt_base\r | |
155 | \r | |
156 | ;TODO: additional plausibility checks\r | |
157 | \r | |
158 | jr z,base_found\r | |
159 | nxt_base:\r | |
160 | ld a,h\r | |
161 | add a,040H\r | |
162 | ld h,a\r | |
163 | jr nc,find_base_loop\r | |
164 | ret ;I/O registers not found\r | |
165 | \r | |
166 | ; Register (base) found.\r | |
167 | \r | |
168 | base_found:\r | |
169 | inc e ; HD64180\r | |
1ffa84bd L |
170 | ld l,RCR ; Disable Refresh Controller\r |
171 | xor a ;\r | |
172 | call reg_out ;\r | |
226d3221 L |
173 | ld l,omcr ; Check, if CPU has OMCR register\r |
174 | ld d,M_IOC ;\r | |
175 | call chk_reg ;\r | |
176 | ret z ; Register does not exist. It's a HD64180\r | |
177 | \r | |
178 | inc e ; Z80180\r | |
179 | ld l,cmr ; Check, if CPU has CMR register\r | |
180 | ld d,M_LNC ;\r | |
181 | call chk_reg ;\r | |
182 | ret z ; register does not exist. It's a Z80180\r | |
183 | \r | |
184 | inc e ; S180/L180 (class) detected.\r | |
185 | \r | |
186 | ret\r | |
187 | \r | |
188 | ;-------------------------------------------------------------------------------\r | |
189 | \r | |
190 | start:\r | |
191 | ld sp,stack\r | |
192 | call check\r | |
193 | \r | |
194 | ld hl,result\r | |
195 | ld (hl),e\r | |
196 | dec hl\r | |
197 | ld (hl),0ffH\r | |
1ffa84bd L |
198 | out (040H),a\r |
199 | \r | |
200 | ; ld a,(wstates)\r | |
201 | ; out0 (DCNTL),a\r | |
202 | ;Z80 Z180(0W) Z180(MaxW)\r | |
203 | loop: ;--------------------------\r | |
204 | in a,(050h) ;11 10 +3*3 19\r | |
205 | jp loop ;10 9 +3*3 18\r | |
206 | ;--------------------------\r | |
207 | ;21 19 37\r | |
208 | \r | |
209 | ; jr loop ;12 8 +2*3 14\r | |
226d3221 L |
210 | \r |
211 | rept 8\r | |
212 | dw 0\r | |
213 | endm\r | |
214 | stack:\r | |
215 | end\r | |
216 | \r | |
217 | ; vim:set ts=8 noet nowrap\r |