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Commit | Line | Data |
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72f58822 L |
1 | /* |
2 | */ | |
3 | ||
4 | #include "common.h" | |
89adce76 | 5 | #include <util/atomic.h> |
72f58822 | 6 | |
89adce76 | 7 | #include "background.h" |
72f58822 L |
8 | #include "serial.h" |
9 | #include "z80-if.h" | |
889202c4 | 10 | #include "debug.h" |
89adce76 | 11 | #include "z180-serv.h" |
72f58822 L |
12 | |
13 | ||
72f58822 L |
14 | |
15 | /*--------------------------------------------------------------------------*/ | |
16 | ||
72f58822 L |
17 | |
18 | uint8_t z80_get_byte(uint32_t adr) | |
19 | { | |
20 | uint8_t data; | |
21 | ||
62f624d3 | 22 | z80_bus_cmd(Request); |
89adce76 | 23 | data = z80_read(adr); |
62f624d3 | 24 | z80_bus_cmd(Release); |
72f58822 L |
25 | |
26 | return data; | |
27 | } | |
28 | ||
29 | ||
30 | /*--------------------------------------------------------------------------*/ | |
31 | ||
32 | struct msg_item { | |
33 | uint8_t fct; | |
34 | uint8_t sub_min, sub_max; | |
35 | void (*func)(uint8_t, int, uint8_t *); | |
36 | }; | |
37 | ||
38 | uint32_t msg_to_addr(uint8_t *msg) | |
39 | { | |
40 | union { | |
41 | uint32_t as32; | |
42 | uint8_t as8[4]; | |
43 | } addr; | |
44 | ||
45 | addr.as8[0] = msg[0]; | |
46 | addr.as8[1] = msg[1]; | |
47 | addr.as8[2] = msg[2]; | |
48 | addr.as8[3] = 0; | |
49 | ||
50 | return addr.as32; | |
51 | } | |
52 | ||
72f58822 L |
53 | |
54 | void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg) | |
55 | { | |
56 | (void)len; | |
57 | ||
89adce76 | 58 | z80_memfifo_init(subf, msg_to_addr(msg)); |
72f58822 L |
59 | } |
60 | ||
61 | ||
62 | void do_msg_char_out(uint8_t subf, int len, uint8_t * msg) | |
63 | { | |
64 | (void)subf; | |
65 | ||
66 | while (len--) | |
67 | putchar(*msg++); | |
68 | } | |
69 | ||
70 | ||
71 | const FLASH struct msg_item z80_messages[] = | |
72 | { | |
73 | { 0, /* fct nr. */ | |
89adce76 | 74 | 1, 3, /* sub fct nr. from, to */ |
72f58822 L |
75 | do_msg_ini_memfifo}, |
76 | { 1, | |
77 | 1, 1, | |
78 | do_msg_char_out}, | |
79 | { 0xff, /* end mark */ | |
80 | 0, 0, | |
81 | 0}, | |
82 | ||
83 | }; | |
84 | ||
85 | ||
86 | ||
87 | ||
88 | void do_message(int len, uint8_t *msg) | |
89 | { | |
90 | uint8_t fct, sub_fct; | |
91 | int_fast8_t i = 0; | |
92 | ||
93 | if (len >= 2) { | |
94 | fct = *msg++; | |
95 | sub_fct = *msg++; | |
96 | len -= 2; | |
97 | ||
89adce76 L |
98 | while (fct != z80_messages[i].fct) { |
99 | if (z80_messages[i].fct == 0xff) { | |
100 | DBG_P(1, "do_message: Unknown function: %i, %i\n", | |
101 | fct, sub_fct); | |
102 | return; /* TODO: unknown message # */ | |
103 | } | |
104 | ||
72f58822 | 105 | ++i; |
72f58822 L |
106 | } |
107 | ||
108 | while (fct == z80_messages[i].fct) { | |
89adce76 L |
109 | if (sub_fct >= z80_messages[i].sub_min && |
110 | sub_fct <= z80_messages[i].sub_max ) | |
72f58822 L |
111 | break; |
112 | ++i; | |
113 | } | |
114 | ||
115 | if (z80_messages[i].fct != fct) { | |
116 | DBG_P(1, "do_message: Unknown sub function: %i, %i\n", | |
117 | fct, sub_fct); | |
118 | return; /* TODO: unknown message sub# */ | |
119 | } | |
120 | ||
121 | (z80_messages[i].func)(sub_fct, len, msg); | |
122 | ||
123 | ||
124 | } else { | |
125 | /* TODO: error */ | |
126 | DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len); | |
127 | } | |
128 | } | |
129 | ||
130 | ||
131 | ||
132 | #define CTRBUF_LEN 256 | |
133 | ||
134 | void check_msg_fifo(void) | |
135 | { | |
136 | int ch; | |
137 | static int_fast8_t state; | |
138 | static int msglen,idx; | |
139 | static uint8_t buffer[CTRBUF_LEN]; | |
140 | ||
89adce76 | 141 | while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) { |
72f58822 L |
142 | switch (state) { |
143 | case 0: /* wait for start of message */ | |
144 | if (ch == 0x81) { | |
145 | msglen = 0; | |
146 | idx = 0; | |
147 | state = 1; | |
148 | } | |
149 | break; | |
150 | case 1: /* get msg len */ | |
151 | if (ch > 0 && ch <= CTRBUF_LEN) { | |
152 | msglen = ch; | |
153 | state = 2; | |
154 | } else | |
155 | state = 0; | |
156 | break; | |
157 | case 2: /* get message */ | |
158 | buffer[idx++] = ch; | |
89adce76 L |
159 | if (idx == msglen) { |
160 | do_message(msglen, buffer); | |
161 | state = 0; | |
162 | } | |
163 | break; | |
164 | } | |
165 | } | |
166 | } | |
167 | ||
168 | ||
169 | int msg_handling(int state) | |
170 | { | |
171 | uint8_t pending; | |
172 | ||
173 | ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { | |
174 | pending = (Stat & S_MSG_PENDING) != 0; | |
175 | Stat &= ~S_MSG_PENDING; | |
176 | } | |
177 | ||
178 | if (pending) { | |
179 | switch (state) { | |
180 | case 0: | |
181 | z80_bus_cmd(Request); | |
182 | uint32_t addr = z80_read(0x40) + | |
183 | ((uint16_t) z80_read(0x41) << 8) + | |
184 | ((uint32_t) z80_read(0x42) << 16); | |
185 | z80_bus_cmd(Release); | |
186 | if (addr != 0) { | |
187 | z80_memfifo_init(fifo_msgin, addr); | |
188 | state = 1; | |
189 | } | |
190 | break; | |
191 | case 1: | |
192 | check_msg_fifo(); | |
72f58822 L |
193 | break; |
194 | } | |
195 | } | |
196 | ||
89adce76 L |
197 | return state; |
198 | } | |
199 | ||
200 | ||
201 | int console_handling(int state) | |
202 | { | |
203 | int ch; | |
204 | uint8_t pending; | |
205 | ||
206 | ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { | |
207 | pending = (Stat & S_CON_PENDING) != 0; | |
208 | Stat &= ~S_CON_PENDING; | |
209 | } | |
210 | ||
211 | if (pending) { | |
212 | while ((ch = z80_memfifo_getc(fifo_conout)) >= 0) { | |
213 | putchar(ch); | |
214 | } | |
72f58822 | 215 | } |
89adce76 L |
216 | |
217 | return state; | |
218 | } | |
219 | ||
220 | ||
221 | ||
222 | ||
223 | static int handle_msg_handling; | |
224 | ||
225 | void setup_z180_serv(void) | |
226 | { | |
227 | ||
228 | handle_msg_handling = bg_register(msg_handling, 0); | |
229 | // bg_register(console_handling, 0); | |
72f58822 L |
230 | } |
231 | ||
89adce76 L |
232 | void restart_z180_serv(void) |
233 | { | |
234 | z80_bus_cmd(Request); | |
235 | z80_write(0x40, 0); | |
236 | z80_write(0x41, 0); | |
237 | z80_write(0x42, 0); | |
238 | z80_bus_cmd(Release); | |
239 | ||
240 | bg_setstat(handle_msg_handling, 0); | |
241 | } | |
72f58822 L |
242 | |
243 | /*--------------------------------------------------------------------------*/ | |
244 | ||
f338df2a | 245 | #if 0 |
72f58822 L |
246 | void dump_mem(const FLASH uint8_t *addr, uint32_t len) |
247 | { | |
248 | DBG_P(1, "hdrom dump:"); | |
249 | while (len) { | |
250 | DBG_P(1, "\n %.5x:", addr); | |
251 | for (unsigned i = 0; i<16; i++) | |
252 | DBG_P(1, " %.2x", *addr++); | |
253 | len -= len > 16 ? 16 : len; | |
254 | } | |
255 | DBG_P(1, "\n"); | |
256 | } | |
f338df2a | 257 | #endif |
72f58822 L |
258 | /*--------------------------------------------------------------------------*/ |
259 | ||
72f58822 L |
260 | |
261 | const FLASH uint8_t iniprog[] = { | |
262 | 0xAF, // xor a | |
263 | 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh | |
264 | 0x3E, 0x30, // ld a,030h | |
265 | 0xED, 0x39, 0x32 //out0 (dcntl),a ;0 mem, max i/0 wait states | |
266 | }; | |
267 | ||
268 | const FLASH uint8_t sertest[] = { | |
269 | 0xAF, // xor a | |
270 | 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh | |
271 | 0x3E, 0x30, // ld a,030h | |
272 | 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states | |
273 | 0x3E, 0x80, // ld a,M_MPBT ;no MP, PS=10, DR=16, SS=0 | |
274 | 0xED, 0x39, 0x03, // out0 (cntlb1),a | |
275 | 0x3E, 0x64, // ld a,M_RE + M_TE + M_MOD2 ; | |
276 | 0xED, 0x39, 0x01, // out0 (cntla1),a | |
277 | 0x3E, 0x00, // ld a,0 | |
278 | 0xED, 0x39, 0x05, // out0 (stat1),a ;Enable rx interrupts | |
279 | 0xED, 0x38, 0x05, //l0:in0 a,(stat1) | |
280 | 0xE6, 0x80, // and 80h | |
281 | 0x28, 0xF9, // jr z,l0 | |
282 | 0xED, 0x00, 0x09, // in0 b,(rdr1) | |
283 | 0xED, 0x38, 0x05, //l1:in0 a,(stat1) | |
284 | 0xE6, 0x02, // and 02h | |
285 | 0x28, 0xF9, // jr z,l1 | |
286 | 0xED, 0x01, 0x07, // out0 (tdr1),b | |
287 | 0x18, 0xEA, // jr l0 | |
288 | }; | |
289 | ||
290 | const FLASH uint8_t test1[] = { | |
291 | 0xAF, // xor a | |
292 | 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh | |
293 | 0x3E, 0x30, // ld a,030h | |
294 | 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states | |
295 | 0x21, 0x1E, 0x00, // ld hl,dmclrt ;load DMA registers | |
296 | 0x06, 0x08, // ld b,dmct_e-dmclrt | |
297 | 0x0E, 0x20, // ld c,sar0l | |
298 | 0xED, 0x93, // otimr | |
299 | 0x3E, 0xC3, // ld a,0c3h ;dst +1, src +1, burst | |
300 | 0xED, 0x39, 0x31, // out0 (dmode),a ; | |
301 | 0x3E, 0x62, // ld a,062h ;enable dma0, | |
302 | 0xED, 0x39, 0x30, //cl_1: out0 (dstat),a ;copy 64k | |
303 | 0x18, 0xFB, // jr cl_1 ; | |
304 | 0x00, 0x00, //dmclrt: dw 0 ;src (inc) | |
305 | 0x00, // db 0 ;src | |
306 | 0x00, 0x00, // dw 0 ;dst (inc), | |
307 | 0x00, // db 0 ;dst | |
308 | 0x00, 0x00, // dw 0 ;count (64k) | |
309 | }; | |
310 | ||
311 | ||
312 |