projects / z180-stamp.git / blame
| Commit | Line | Data |
|---|---|---|
| 2fe44122 L |
1 | page 200\r |
| 2 | \r | |
| 3 | extrn ioiniml\r | |
| 4 | \r | |
| 5 | global as0init\r | |
| 6 | global as0ista,as0inp\r | |
| 7 | global as0osta,as0out\r | |
| 8 | global as1init\r | |
| 9 | global as1ista,as1inp\r | |
| 10 | global as1osta,as1out\r | |
| 11 | \r | |
| 12 | include config.inc\r | |
| 13 | include z180reg.inc\r | |
| 14 | \r | |
| 15 | \r | |
| 16 | ;-----------------------------------------------------\r | |
| 17 | ;\r | |
| 18 | ;\r | |
| 19 | ; TC = (f PHI /(2*baudrate*Clock_mode)) - 2\r | |
| 20 | ;\r | |
| 21 | ; TC = (f PHI / (32 * baudrate)) - 2\r | |
| 22 | ;\r | |
| 23 | \r | |
| 24 | cseg\r | |
| 25 | ;\r | |
| 26 | ; Init Serial I/O for console input and output (ASCI1)\r | |
| 27 | ;\r | |
| 28 | \r | |
| 29 | \r | |
| 30 | \r | |
| 31 | as0init:\r | |
| 32 | ld hl,initab0\r | |
| 33 | jp ioiniml\r | |
| 34 | \r | |
| 35 | as1init:\r | |
| 36 | ld hl,initab1\r | |
| 37 | jp ioiniml\r | |
| 38 | \r | |
| 39 | \r | |
| 40 | ld a,M_MPBT \r | |
| 41 | out0 (cntlb1),a\r | |
| 42 | ld a,M_RE + M_TE + M_MOD2 ;Rx/Tx enable \r | |
| 43 | out0 (cntla1),a\r | |
| 44 | ld a,M_RIE\r | |
| 45 | out0 (stat1),a ;Enable rx interrupts\r | |
| 46 | \r | |
| 47 | ret ;\r | |
| 48 | \r | |
| 49 | \r | |
| 50 | initab0:\r | |
| 51 | db 1,stat0,0 ;Disable rx/tx interrupts\r | |
| 52 | ;Enable baud rate generator\r | |
| 53 | db 1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS\r | |
| 54 | db 2,astc0l,low 28, high 28\r | |
| 55 | db 1,cntlb0,M_MPBT ;No MP Mode, X16\r | |
| 56 | db 1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r | |
| 57 | db 0\r | |
| 58 | \r | |
| 59 | initab1:\r | |
| 60 | db 1,stat1,0 ;Disable rx/tx ints, disable CTS1\r | |
| 61 | db 1,asext1,M_BRGMOD ;Enable baud rate generator\r | |
| 62 | db 2,astc1l,low 3, high 3\r | |
| 63 | db 1,cntlb1,M_MPBT ;No MP Mode, X16\r | |
| 64 | db 1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r | |
| 65 | db 0\r | |
| 66 | \r | |
| 67 | \r | |
| 68 | \r | |
| 69 | as0ista:\r | |
| 70 | in0 a,(stat0)\r | |
| 71 | and M_RDRF\r | |
| 72 | ret z\r | |
| 73 | or 0ffh\r | |
| 74 | ret\r | |
| 75 | \r | |
| 76 | as1ista:\r | |
| 77 | in0 a,(stat1)\r | |
| 78 | and M_RDRF\r | |
| 79 | ret z\r | |
| 80 | or 0ffh\r | |
| 81 | ret\r | |
| 82 | \r | |
| 83 | \r | |
| 84 | as0inp:\r | |
| 85 | in0 a,(stat0)\r | |
| 86 | rlca\r | |
| 87 | jr nc,as0inp\r | |
| 88 | in0 a,rdr0\r | |
| 89 | ret\r | |
| 90 | \r | |
| 91 | as1inp:\r | |
| 92 | in0 a,(stat1)\r | |
| 93 | rlca\r | |
| 94 | jr nc,as1inp\r | |
| 95 | in0 a,rdr1\r | |
| 96 | ret\r | |
| 97 | \r | |
| 98 | \r | |
| 99 | \r | |
| 100 | as0osta:\r | |
| 101 | in0 a,(stat0)\r | |
| 102 | and M_TDRE\r | |
| 103 | ret z\r | |
| 104 | or 0ffh\r | |
| 105 | ret\r | |
| 106 | \r | |
| 107 | as1osta:\r | |
| 108 | in0 a,(stat1)\r | |
| 109 | and M_TDRE\r | |
| 110 | ret z\r | |
| 111 | or 0ffh\r | |
| 112 | ret\r | |
| 113 | \r | |
| 114 | \r | |
| 115 | as0out:\r | |
| 116 | in0 a,(stat0)\r | |
| 117 | and M_TDRE\r | |
| 118 | jr z,as0out\r | |
| 119 | out0 (tdr0),c\r | |
| 120 | ld a,c\r | |
| 121 | ret\r | |
| 122 | \r | |
| 123 | as1out:\r | |
| 124 | in0 a,(stat1)\r | |
| 125 | and M_TDRE\r | |
| 126 | jr z,as1out\r | |
| 127 | out0 (tdr1),c\r | |
| 128 | ld a,c\r | |
| 129 | ret\r | |
| 130 | \r | |
| 131 | end\r | |
| 132 | \r | |
| 133 | \r |