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Commit | Line | Data |
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a16ba2b0 L |
1 | page 200\r |
2 | \r | |
3 | \r | |
4 | extrn buf.init\r | |
5 | extrn isv_sw\r | |
6 | \r | |
e4c4b148 | 7 | \r |
a16ba2b0 | 8 | global ser.init\r |
30d1329e L |
9 | global ser.ist,ser.in\r |
10 | global ser.ost,ser.out\r | |
a16ba2b0 | 11 | \r |
e4c4b148 | 12 | ;TODO: define a trampoline area somewhere in top ram.\r |
a16ba2b0 L |
13 | rtxisvjmp equ 0FF60h ;momentan frei...\r |
14 | \r | |
15 | include config.inc\r | |
16 | include z180reg.inc\r | |
17 | \r | |
18 | \r | |
19 | ;-----------------------------------------------------\r | |
20 | \r | |
21 | dseg\r | |
e4c4b148 | 22 | \r |
a16ba2b0 | 23 | buf_start:\r |
e4c4b148 L |
24 | mkbuf s1.rx_id, ser1.inbuf, s1.rx_len\r |
25 | mkbuf s1.tx_id, ser1.outbuf, s1.tx_len\r | |
a16ba2b0 L |
26 | buf_end:\r |
27 | \r | |
28 | \r | |
29 | \r | |
30 | ;-----------------------------------------------------\r | |
31 | \r | |
32 | cseg\r | |
33 | ;\r | |
34 | ; Init Serial I/O for console input and output (ASCI1)\r | |
35 | ;\r | |
e4c4b148 | 36 | \r |
a16ba2b0 L |
37 | \r |
38 | ser.init:\r | |
39 | ; ld a,i\r | |
40 | ; push af ;save IFF\r | |
41 | ; di\r | |
42 | \r | |
43 | xor a ;\r | |
44 | out0 (stat1),a ;Disable rx/tx interrupts\r | |
e4c4b148 | 45 | \r |
a16ba2b0 L |
46 | ld hl,rxtx_src ;move rx and tx isv to common ram\r |
47 | ld de,rxtx_dst ;\r | |
e4c4b148 | 48 | ld bc,rxtx_src_e-rxtx_src ;\r |
a16ba2b0 L |
49 | ldir ;\r |
50 | \r | |
51 | ld hl,rtxisvjmp ;rx/tx int vector\r | |
52 | ld (ivtab + IV$ASCI1),hl;\r | |
53 | ld a,0cdh ;\r | |
54 | ld (rtxisvjmp),a ;\r | |
55 | ld hl,isv_sw ;\r | |
56 | ld (rtxisvjmp + 1),hl ;\r | |
57 | ld hl,rxtxisv ;\r | |
58 | ld (rtxisvjmp + 3),hl ;\r | |
59 | \r | |
60 | ; ASCI1: 8N1, highest baudrate (56700), CTS disabled\r | |
61 | \r | |
e4c4b148 | 62 | ld a,M_MPBT\r |
a16ba2b0 L |
63 | out0 (cntlb1),a\r |
64 | ld a,M_RE + M_TE + M_MOD2\r | |
65 | out0 (cntla1),a\r | |
66 | ld a,M_RIE\r | |
67 | out0 (stat1),a ;Enable rx interrupts\r | |
68 | \r | |
69 | ld ix,ser1.inbuf\r | |
70 | ld a,ser1.inbuf.mask\r | |
71 | call buf.init\r | |
72 | ld ix,ser1.outbuf\r | |
73 | ld a,ser1.outbuf.mask\r | |
74 | call buf.init\r | |
75 | \r | |
76 | ; pop af\r | |
77 | ; ret po\r | |
78 | ; ei\r | |
79 | ret ;\r | |
80 | \r | |
30d1329e | 81 | ser.ist:\r |
a16ba2b0 L |
82 | push ix\r |
83 | ld ix,ser1.inbuf ;\r | |
84 | \r | |
85 | buf.empty:\r | |
86 | ld a,(ix+o.in_idx) ;\r | |
87 | sub (ix+o.out_idx) ;\r | |
88 | pop ix\r | |
89 | ret z\r | |
90 | or 0ffh\r | |
91 | ret\r | |
e4c4b148 | 92 | \r |
a16ba2b0 | 93 | ser.in:\r |
e4c4b148 | 94 | push hl ;11\r |
a16ba2b0 | 95 | push de ;11\r |
e4c4b148 | 96 | ld hl,ser1.inbuf-1 ; 9 hl = &rx.out_idx\r |
a16ba2b0 L |
97 | ld a,(hl) ; 6 a = rx.out_idx\r |
98 | dec hl ; 4 hl = &rx.in_idx\r | |
99 | jr bg.w1\r | |
100 | bg.wait:\r | |
101 | halt\r | |
102 | bg.w1:\r | |
e4c4b148 | 103 | cp (hl) ; 6 while (out_idx==in_idx)\r |
a16ba2b0 L |
104 | jr z,bg.wait ; 6 (/8) ;\r |
105 | \r | |
e4c4b148 | 106 | ld e,a ; 4\r |
a16ba2b0 | 107 | ld d,0 ; 6\r |
4caee1ec L |
108 | inc de\r |
109 | inc de\r | |
a16ba2b0 L |
110 | \r |
111 | ex de,hl ; 3\r | |
112 | add hl,de ;10\r | |
113 | ld l,(hl) ; 6\r | |
e4c4b148 | 114 | ex de,hl ; 3\r |
4caee1ec L |
115 | \r |
116 | inc a ; 4\r | |
a16ba2b0 | 117 | dec hl ; 4\r |
e4c4b148 | 118 | and (hl) ; 6\r |
a16ba2b0 L |
119 | inc hl ; 4\r |
120 | inc hl ; 4\r | |
121 | ld (hl),a ; 7\r | |
e4c4b148 | 122 | \r |
a16ba2b0 L |
123 | ld a,e ; 4\r |
124 | pop de ; 9\r | |
125 | pop hl ; 9\r | |
126 | ret ; 9\r | |
e4c4b148 | 127 | ; 153\r |
a16ba2b0 | 128 | \r |
30d1329e | 129 | ser.ost:\r |
a16ba2b0 L |
130 | push ix\r |
131 | ld ix,ser1.outbuf ;\r | |
132 | buf.full:\r | |
133 | ld a,(ix+o.in_idx) ;\r | |
134 | inc a\r | |
135 | and (ix+o.mask)\r | |
136 | sub (ix+o.out_idx) ;\r | |
137 | pop ix\r | |
138 | ret z\r | |
139 | or 0ffh\r | |
140 | ret\r | |
141 | \r | |
142 | \r | |
143 | ser.out:\r | |
144 | push ix\r | |
145 | ld ix,ser1.outbuf ;\r | |
146 | buf.put:\r | |
147 | push hl ;\r | |
148 | push bc\r | |
149 | push ix\r | |
150 | pop hl\r | |
30d1329e | 151 | ld a,c\r |
a16ba2b0 L |
152 | ld c,(ix+o.in_idx) ;\r |
153 | ld b,0\r | |
154 | add hl,bc\r | |
4caee1ec | 155 | ld (hl),a\r |
a16ba2b0 L |
156 | \r |
157 | ld a,c ;\r | |
158 | inc a\r | |
159 | and (ix+o.mask)\r | |
160 | bp.wait:\r | |
161 | cp (ix+o.out_idx) ;\r | |
162 | jr z,bp.wait\r | |
a16ba2b0 L |
163 | ld (ix+o.in_idx),a\r |
164 | \r | |
165 | di ;036f\r | |
166 | in0 a,(stat1) ;0374\r | |
167 | set TIE,a ;0377\r | |
168 | out0 (stat1),a ;0379\r | |
169 | ei ;037c\r | |
170 | \r | |
171 | ld a,b\r | |
172 | pop bc\r | |
173 | pop hl\r | |
174 | pop ix\r | |
175 | ret\r | |
176 | \r | |
177 | \r | |
178 | ;------------------------------------------\r | |
179 | ; ASCI 1 Transmit/Receive interupt routines\r | |
180 | ; moved to common ram\r | |
181 | \r | |
182 | rxtx_src:\r | |
183 | dseg\r | |
184 | rxtx_dst: ; (0c097h) old\r | |
185 | \r | |
186 | rxtxisv:\r | |
187 | inidat\r | |
188 | in0 a,(stat1) ;receive flag set?\r | |
189 | jp p,txisv ;\r | |
190 | \r | |
191 | in0 d,(rdr1) ;todo: break detection\r | |
192 | bit FE,a ;framing error?\r | |
193 | jr nz,??ri_1\r | |
e4c4b148 | 194 | \r |
a16ba2b0 L |
195 | push ix\r |
196 | ld ix,ser1.inbuf ;\r | |
197 | ld hl,ser1.inbuf ;\r | |
198 | ld c,(ix+o.in_idx) ;\r | |
199 | ld b,0\r | |
200 | add hl,bc\r | |
201 | \r | |
202 | ld a,c ;\r | |
203 | inc a\r | |
204 | and (ix+o.mask)\r | |
205 | cp (ix+o.out_idx) ;\r | |
206 | jr z,??ri_0\r | |
207 | ld (hl),d\r | |
208 | ld (ix+o.in_idx),a\r | |
209 | ??ri_0:\r | |
210 | pop ix\r | |
211 | ??ri_1:\r | |
212 | in0 a,(cntla1) ;0705 c0c0\r | |
213 | res EFR,a ;0708\r | |
214 | out0 (cntla1),a ;070a\r | |
215 | ret\r | |
216 | \r | |
217 | inidate\r | |
218 | \r | |
219 | txisv:\r | |
220 | inidat\r | |
221 | push ix\r | |
222 | ld ix,ser1.outbuf ;\r | |
223 | \r | |
224 | ld a,(ix+o.out_idx) ;\r | |
225 | cp (ix+o.in_idx) ;\r | |
226 | jr z,??ti_2\r | |
227 | \r | |
228 | ld hl,ser1.outbuf ;\r | |
229 | add a,l\r | |
230 | ld l,a\r | |
231 | jr nc,??ti_1\r | |
232 | inc h\r | |
233 | ??ti_1:\r | |
234 | ld l,(hl)\r | |
235 | out0 (tdr1),l ;071b\r | |
e4c4b148 | 236 | \r |
a16ba2b0 L |
237 | ld a,(ix+o.out_idx) ;\r |
238 | inc a\r | |
239 | and (ix+o.mask)\r | |
240 | ld (ix+o.out_idx),a\r | |
241 | jr ??ti_3\r | |
242 | ??ti_2:\r | |
243 | in0 a,(stat1) ;0730 disable tx-int\r | |
244 | res TIE,a ;0733\r | |
245 | out0 (stat1),a ;0735\r | |
246 | ??ti_3:\r | |
247 | pop ix\r | |
248 | ret\r | |
249 | \r | |
250 | inidate\r | |
251 | \r | |
252 | cseg\r | |
253 | rxtx_src_e:\r | |
254 | \r | |
255 | \r | |
256 | end\r |