[z180-stamp.git] / avr / cmd_cpu.c

/*
 * (C) Copyright 2018 Leo C. <erbl259-lmu@yahoo.de>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include "cmd_cpu.h"
//#include <ctype.h>
#include <util/atomic.h>

#include "z80-if.h"
#include "con-utils.h"
#include "env.h"
#include "eval_arg.h"
#include "timer.h"
#include "getopt-min.h"
#include "debug.h"

/* hack to get Z180 loadfile into flash memory */
#define const const FLASH
#include "../z180/cpuinfo.h"
#undef const

#define DEBUG_CPU	1	/* set to 1 to debug */

#define debug_cpu(fmt, args...)		                                              \
	debug_cond(DEBUG_CPU, fmt, ##args)


/*
 * delay for <count> ms...
 */
static void	test_delay(uint32_t count)
{
	uint32_t ts = get_timer(0);

	while (get_timer(ts) <= count);
}

static uint32_t z80_measure_phi(uint_fast8_t cycles)
{
	uint16_t ref_stop;
	uint16_t ref_ovfl;
	uint8_t x_ovfl;
	uint32_t x_freq;


	PRR1 &= ~_BV(PRTIM3);
	TCCR3A = 0;
	TCCR3B = 0b000<<CS30;	/* stop counter */
	TCNT3 = 0;
	x_ovfl = 0;
	TIFR3 = _BV(TOV3);
	ref_ovfl = 0;

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		/* Reset pending int */
		EIFR = _BV(INTF6);
		/* Wait for falling edge */
		while ((EIFR & _BV(INTF6)) == 0)
			;
		TCCR3B = 0b110<<CS30;	/* Count falling edges on T3 (==INT6) */
		OCR4B = TCNT4;
		TIFR4 = _BV(OCF4B);		/* clear compare match flag */
	}
	while (ref_ovfl < 60) {
		ATOMIC_BLOCK(ATOMIC_FORCEON) {
			if ((TIFR4 & _BV(OCF4B)) != 0) {
				TIFR4 = _BV(OCF4B);
				ref_ovfl++;
			}
			if ((TIFR3 & _BV(TOV3)) != 0) {
				TIFR3 = _BV(TOV3);
				x_ovfl++;
			}
		}
	}

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		EIFR = _BV(INTF6);
		for (;;) {
			if (EIFR & _BV(INTF6)) {
				TCCR3B = 0b000<<CS30;	/* stop counter */
				ref_stop = TCNT4;
				break;
			}
			if ((TIFR4 & _BV(OCF4B)) != 0) {
				TIFR4 = _BV(OCF4B);
				ref_ovfl++;
			}
		}
	}

	if ((TIFR3 & _BV(TOV3)) != 0) {
		TIFR3 = _BV(TOV3);
		x_ovfl++;
	}

	uint32_t ref_cnt = (ref_stop - OCR4B) + ((uint32_t)ref_ovfl << 16);
	uint32_t x_cnt = TCNT3 + ((uint32_t) x_ovfl << 16);
	uint64_t x_tmp = (uint64_t) 100000 * (x_cnt * cycles);

	debug_cpu("TCNT3: %6u, ref_cnt: %9lu\n", TCNT3, ref_cnt);
	debug_cpu("x_tmp: %lu %lu\n", (uint32_t) (x_tmp >> 32), (uint32_t) (x_tmp & 0xffffffff));

	x_tmp = (x_tmp * getenv_ulong(PSTR(ENV_FMON), 10, F_CPU) + (ref_cnt / 2)) / ref_cnt;

	debug_cpu("x_tmp: %lu %lu\n", (uint32_t) (x_tmp >> 32), (uint32_t) (x_tmp & 0xffffffff));

	/* round to 5 decimal digits */
	int_fast8_t sc = 5;
	while (sc > 0 || x_tmp >= 100000) {
		x_tmp = (x_tmp + 5)/10;
	    sc--;
	}
	x_freq = x_tmp;
	while (sc < 0) {
		x_freq *= 10;
	    sc++;
	}

	/* Stop Timer */
	TCCR3B = 0;
	PRR1 |= _BV(PRTIM3);

	return x_freq;
}

static const FLASH uint8_t loop_code[] = {
/* 0000 */  0x00,             /* nop                                        */
/* 0001 */  0xAF,             /* xor  a                                     */
/* 0005 */  0xD3,0x32,        /* out  (032h),a  ;DCNTL                      */
/* 0002 */  0xD3,0x36,        /* out  (036h),a  ;RCR                        */
/*      */                    /*                                            */
/* 0006 */  0xD3,0x40,        /* out  (040H),a  ;Ready                      */
/*      */                    /*                                            */
/*      */                    /*                ;Z80    Z180(0W) Z180(MaxW) */
/* 0008 */                    /* loop:          ;-------------------------- */
/* 0008 */  0xDB,0x50,        /* in   a,(050h)  ;11       10     +3*3  19   */
/* 000A */  0xC3,0x08,0x00    /* jp   loop      ;10        9     +3*3  18   */
                              /*                ;-------------------------- */
                              /*                ;21       19           37   */
};

command_ret_t do_cpu_freq(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char * const argv[])
{

#define O_SILENT		(1<<0)
#define O_WENV			(1<<1)
#define O_LOAD_LOOP     (1<<2)
#define O_UNLOAD_LOOP   (1<<3)

	uint_fast8_t options = O_LOAD_LOOP | O_UNLOAD_LOOP;
	uint_fast8_t lcycles = 19;
	uint16_t timeout = 1000;
	uint8_t eimsk_save;

	uint8_t mem_save[ARRAY_SIZE(loop_code)];

	int opt;
	while ((opt = getopt(argc, argv, PSTR("swnuc:t:"))) != -1) {
		switch (opt) {
		case 's':
			options |= O_SILENT;
			break;
		case 'w':
			options |= O_WENV;
			break;
		case 'n':
			options &= ~O_LOAD_LOOP;
			break;
		case 'u':
			options &= ~O_UNLOAD_LOOP;
			break;
		case 'c':
			lcycles = eval_arg(optarg, NULL);
			break;
		case 't':
			timeout = eval_arg(optarg, NULL);
			break;
		default: /* '?' */
			return CMD_RET_USAGE;
		}
	}
	if (argc - optind != 0)
		return CMD_RET_USAGE;

	if (z80_bus_state() & ZST_RUNNING) {
		if (!(options & O_SILENT))
			printf_P(PSTR("Frequency measuring failed. CPU allready running!\n"));
		return CMD_RET_FAILURE;
	}

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		/* Save state and disable INT5/INT6 */
		eimsk_save = EIMSK;
		EIMSK &= ~_BV(INT6);
		EIMSK &= ~_BV(INT5);
	}

	z80_bus_cmd(Request);
	if (options & O_LOAD_LOOP) {
		z80_read_block(mem_save, 0, ARRAY_SIZE(loop_code));
		z80_write_block_P(loop_code, 0, ARRAY_SIZE(loop_code));
	}
	EIFR = _BV(INTF5);				/* Reset pending int */
	z80_bus_cmd(Release);
	z80_bus_cmd(Run);

	clear_ctrlc();					/* forget any previous Control C */
	ERRNUM err = 0;

	/* Wait for falling edge */
	do {
		/* check for ctrl-c to abort... */
		if (had_ctrlc() || ctrlc()) {
			err = EINTR;
			break;
		}
	} while ((EIFR & _BV(INTF5)) == 0);

	uint32_t cpu_freq = 0;
	if (!err)
		cpu_freq = z80_measure_phi(lcycles);

	z80_bus_cmd(Reset);
	if (options & O_UNLOAD_LOOP) {
		z80_bus_cmd(Request);
		z80_write_block(mem_save, 0, ARRAY_SIZE(loop_code));
		z80_bus_cmd(Release);
	}
	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		/* Restore INT5/INT6 */
		if ((eimsk_save & _BV(INT5)) != 0)
			EIMSK |= _BV(INT5);
		if ((eimsk_save & _BV(INT6)) != 0)
			EIMSK |= _BV(INT6);
		/* Reset pending int */
		EIFR = _BV(INTF5);
		EIFR = _BV(INTF6);
	}

	Stat &= ~S_MSG_PENDING;
	Stat &= ~S_CON_PENDING;

	if (err)
		cmd_error(CMD_RET_FAILURE, err, NULL);

	if (!(options & O_SILENT)) {
		uint8_t sc = cpu_freq >> 28;
		printf_P(PSTR("%lu %3u\n"), cpu_freq & 0x0fffffff, sc);
	}
#if 0
	if (options & O_WENV) {
		if (setenv_ulong(PSTR(ENV_CPU_FREQ), cpu_freq)) {
			if (!(options & O_SILENT))
				printf_P(PSTR("'SETENV (%S, %lu)' failed!\n"), PSTR(ENV_CPU_FREQ), cpu_freq);
			return CMD_RET_FAILURE;
		}
	}
#endif
	return CMD_RET_SUCCESS;
}

static const FLASH char * const FLASH cpu_strings[] = {
	FSTR("Unknown"),
	FSTR("8080"),
	FSTR("8085"),
	FSTR("Z80"),
	FSTR("x180"),
	FSTR("HD64180"),
	FSTR("Z80180"),
	FSTR("Z80S180"),
};

command_ret_t do_cpuchk(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char * const argv[] UNUSED)
{
	uint_fast8_t cputype = 0;
	ERRNUM err = ESUCCESS;
	uint8_t eimsk_save;
	uint8_t ram_save[cpuinfo_length];

	if (z80_bus_state() & ZST_RUNNING) {
		err = ERUNNING;
	} else {
		z80_bus_request_or_exit();
		z80_read_block(ram_save, 0, cpuinfo_length);
		z80_load_mem(0, cpuinfo,
					&cpuinfo_sections,
					cpuinfo_address,
					cpuinfo_length_of_sections);
		z80_bus_cmd(Release);

		if (argv[1] && (argv[1][0] == 'n'))
			goto donot;

		ATOMIC_BLOCK(ATOMIC_FORCEON) {
			/* Save state and disable INT5/INT6 */
			eimsk_save = EIMSK;
			EIMSK &= ~_BV(INT6);
			EIMSK &= ~_BV(INT5);
		}
		EIFR = _BV(INTF5);				/* Reset pending int */
		z80_bus_cmd(Run);

		clear_ctrlc();		/* forget any previous Control C */
		do {
			/* check for ctrl-c to abort... */
			if (had_ctrlc() || ctrlc()) {
				err = EINTR;
				break;
			}
		} while ((EIFR & _BV(INTF5)) == 0);
		z80_bus_cmd(Reset);
		ATOMIC_BLOCK(ATOMIC_FORCEON) {
			/* Restore INT5/INT6 */
			if ((eimsk_save & _BV(INT5)) != 0)
				EIMSK |= _BV(INT5);
			if ((eimsk_save & _BV(INT6)) != 0)
				EIMSK |= _BV(INT6);
			/* Reset pending int */
			EIFR = _BV(INTF5);
			EIFR = _BV(INTF6);
		}
		Stat &= ~S_MSG_PENDING;
		Stat &= ~S_CON_PENDING;
		z80_bus_cmd(Request);
		if (z80_read(3) == 0xFF) {
			cputype = z80_read(4);
		}
		z80_write_block(ram_save, 0, cpuinfo_length);
		z80_bus_cmd(Release);
	}

donot:

	if (err)
		cmd_error(CMD_RET_FAILURE, err, NULL);

	if (cputype >= ARRAY_SIZE(cpu_strings))
		cputype = 0;
	printf_P(PSTR("Detected CPU: %S\n"), cpu_strings[cputype]);

	return CMD_RET_SUCCESS;
}

command_ret_t do_cpu_test(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char * const argv[])
{

	uint32_t pulsewidth = 10; /* ms */

	int opt;
	while ((opt = getopt(argc, argv, PSTR("t:"))) != -1) {
		switch (opt) {
		case 't':
			pulsewidth = eval_arg(optarg, NULL);
			break;
		default: /* '?' */
			return CMD_RET_USAGE;
		}
	}

	if ((z80_bus_state() & ZST_ACQUIRED) != RESET)
		cmd_error(CMD_RET_FAILURE, ERUNNING, NULL);

	clear_ctrlc();		/* forget any previous Control C */
	do {
		z80_bus_cmd(Request);
		test_delay(pulsewidth);
		z80_bus_cmd(Release);
		test_delay(pulsewidth);
	} while (!(had_ctrlc() || ctrlc()));

	return CMD_RET_SUCCESS;
}

command_ret_t do_bus_test(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char * const argv[] UNUSED)
{
	int ch;

#if 0
	int opt;
	while ((opt = getopt(argc, argv, PSTR("t:"))) != -1) {
		switch (opt) {
		case 't':
			pulsewidth = eval_arg(optarg, NULL);
			break;
		default: /* '?' */
			return CMD_RET_USAGE;
		}
	}
#endif

	my_puts_P(PSTR(
		"  1:  RESET         4:  RUN           r:  Toggle /RESET\n"
		"  2:  REQUEST       5:  RESTART       b:  Toggle /BUSREQ\n"
		"  3:  RELEASE       6:  M_CYCLE\n"
		"\n"
		//"Bus state: "
	));

	do {
		ch = my_getchar(1);
		if (ch >= 0) {
			switch (ch) {
				case '1':		/* bus_cmd RESET   */
				case '2':		/* bus_cmd REQUEST */
				case '3':		/* bus_cmd RELEASE */
				case '4':		/* bus_cmd RUN     */
				case '5':		/* bus_cmd RESTART */
				case '6':		/* bus_cmd M_CYCLE */
						z80_bus_cmd(ch - '1' + Reset);
						break;
				case 'r':		/* Toggle RESET    */
						z80_toggle_reset();
						break;
				case 'b':		/* Toggle BUSREQ   */
						z80_toggle_busreq();
						break;
			}
			test_delay(10);
			uint32_t cycles = z80_get_busreq_cycles();
			printf_P(PSTR("\rState: %.2x, cycles: %lu, time: %luus      "),
					z80_bus_state(), cycles, (uint32_t) (cycles * 1000000LL / F_CPU));
		}
	} while (ch != 0x03);

	putchar('\n');
	return CMD_RET_SUCCESS;
}

command_ret_t do_busack_test(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char * const argv[] UNUSED)
{

	if ((z80_bus_state() & ZST_ACQUIRED) != RESET)
		cmd_error(CMD_RET_FAILURE, ERUNNING, NULL);

	z80_bus_cmd(Request);
	uint32_t result = z80_get_busreq_cycles();
	test_delay(20);
	z80_bus_cmd(Release);

#if 0
	long div;

	pinconf = gpio_config_get(pin);
	if (pinconf == OUTPUT_TIMER) {
		div = gpio_clockdiv_get(pin);
	}
#endif


	printf_P(PSTR("cycles: %lu, time: %luus\n"), result, (uint32_t) (result * 1000000LL / F_CPU));

	return CMD_RET_SUCCESS;
}


/*
 * command table for subcommands
 */

cmd_tbl_t cmd_tbl_cpu[] = {
CMD_TBL_ITEM(
	chkcpu,	CONFIG_SYS_MAXARGS,	CTBL_RPT|CTBL_SUBCMDAUTO, do_cpuchk,
	"Check/Identify CPU",
	""
),
CMD_TBL_ITEM(
	buscmd,	CONFIG_SYS_MAXARGS,	CTBL_RPT,	do_bus_test,
	"Bus commands",
	""
),
CMD_TBL_ITEM(
	test,	CONFIG_SYS_MAXARGS,	1,	do_cpu_test,
	"Do bus request/release cycles",
	"[-t pulsewidth]"
),
CMD_TBL_ITEM(
	busack,	2,	1,	do_busack_test,
	"Get time from /Reset high to /BUSACK low",
	""
),
CMD_TBL_ITEM(
	freq,	CONFIG_SYS_MAXARGS,	1,	do_cpu_freq,
	"Measure cpu frequency",
	"[-qwn] [-c loopcycles] [-t timeout]\n"
	"     -q Be quiet\n"
//	"     -w  Write result to environment variable '"ENV_CPU_FREQ"'"
),

CMD_TBL_ITEM(
	help,	CONFIG_SYS_MAXARGS,	CTBL_RPT,	do_help,
	"Print sub command description/usage",
	"\n"
	"       - print brief description of all sub commands\n"
	"fat help command ...\n"
	"       - print detailed usage of sub cmd 'command'"
),

/* This does not use the CMD_TBL_ITEM macro as ? can't be used in symbol names */
	{FSTR("?"),   CONFIG_SYS_MAXARGS, 1, do_help,
	 NULL,
#ifdef  CONFIG_SYS_LONGHELP
	FSTR(""),
#endif /* CONFIG_SYS_LONGHELP */
	NULL,
#ifdef CONFIG_AUTO_COMPLETE
	NULL,
#endif
},
/* Mark end of table */
CMD_TBL_END(cmd_tbl_cpu)
};


command_ret_t do_cpu(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char * const argv[] UNUSED)
{
	//puts_P(PSTR("Huch?"));

	return CMD_RET_USAGE;
}


#if 0		/* Z180 Single Step Functions */
/*
 * Z180 Single Step Functions
 *
 */


#define P_RUN		PORTG
#define RUN			1
#define DDR_RUN		DDRG
#define P_STEP		PORTG
#define STEP		0
#define DDR_STEP	DDRG
#define P_WAIT		PORTG
#define WAIT		2
#define DDR_WAIT	DDRG
/* All three signals are on the same Port (PortG) */
#define PORT_SS		PORTG
#define DDR_SS		DDRG
#define PIN_SS		PING

static bool ss_available;

int single_step_setup(void)
{
	ss_available = false;

#if 0
	if (z80_bus_state() & ZST_RUNNING ||
			!(z80_bus_cmd(Request) & ZST_ACQUIRED))
		return  -1;
#endif

	/* STEP, RUN output, WAIT input */

	PORT_SS |= _BV(RUN) | _BV(STEP);
	DDR_SS |= _BV(RUN) | _BV(STEP);
	DDR_SS &= ~_BV(WAIT);

	/* RUN high, MREQ pulse --> WAIT should be low */
	z80_mreq_pulse();

	if ((PIN_SS & _BV(WAIT)) == 0) {

		/* RUN high, STEP pulse --> WAIT should be high */
		PIN_SS = _BV(STEP);
		PIN_SS = _BV(STEP);
		if ((PIN_SS & _BV(WAIT)) != 0) {

			/* RUN high, MREQ pulse --> WAIT should be low */
			z80_mreq_pulse();
			if ((PIN_SS & _BV(WAIT)) == 0) {

				/* RUN low --> WAIT should be high */
				PIN_SS = _BV(RUN);
				if ((PIN_SS & _BV(WAIT)) != 0) {

					/* RUN low, STEP pulse --> WAIT should be high */
					PIN_SS = _BV(STEP);
					PIN_SS = _BV(STEP);
					if ((PIN_SS & _BV(WAIT)) != 0) {

						/* all tests passed */
						ss_available = true;
					}
				}
			}
		}
	}

	if (!ss_available) {
		DDR_SS &= ~(_BV(STEP) | _BV(RUN));
		PORT_SS |= _BV(RUN) | _BV(STEP);
	}

	return ss_available ? 0 : -1;
}
#endif
Commit	Line	Data
226d3221 L	1	/*
	2	* (C) Copyright 2018 Leo C. <erbl259-lmu@yahoo.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
	7	#include "cmd_cpu.h"
	8	//#include <ctype.h>
dbc1de70	9	#include <util/atomic.h>
226d3221 L	10
	11	#include "z80-if.h"
	12	#include "con-utils.h"
2c60e1dc	13	#include "env.h"
51dd0948 L	14	#include "eval_arg.h"
	15	#include "timer.h"
	16	#include "getopt-min.h"
2c60e1dc	17	#include "debug.h"
226d3221 L	18
	19	/* hack to get Z180 loadfile into flash memory */
	20	#define const const FLASH
	21	#include "../z180/cpuinfo.h"
	22	#undef const
	23
aea51b6c L	24	#define DEBUG_CPU 1 /* set to 1 to debug */
	25
	26	#define debug_cpu(fmt, args...) \
	27	debug_cond(DEBUG_CPU, fmt, ##args)
	28
226d3221	29
dbc1de70 L	30	/*
	31	* delay for <count> ms...
	32	*/
	33	static void test_delay(uint32_t count)
	34	{
	35	uint32_t ts = get_timer(0);
	36
	37	while (get_timer(ts) <= count);
	38	}
	39
aea51b6c	40	static uint32_t z80_measure_phi(uint_fast8_t cycles)
dbc1de70 L	41	{
	42	uint16_t ref_stop;
	43	uint16_t ref_ovfl;
24ba732a	44	uint8_t x_ovfl;
24ba732a L	45	uint32_t x_freq;
	46
	47
24ba732a L	48	PRR1 &= ~_BV(PRTIM3);
	49	TCCR3A = 0;
	50	TCCR3B = 0b000<<CS30; /* stop counter */
	51	TCNT3 = 0;
	52	x_ovfl = 0;
	53	TIFR3 = _BV(TOV3);
	54	ref_ovfl = 0;
	55
	56	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	57	/* Reset pending int */
	58	EIFR = _BV(INTF6);
	59	/* Wait for falling edge */
	60	while ((EIFR & _BV(INTF6)) == 0)
	61	;
	62	TCCR3B = 0b110<<CS30; /* Count falling edges on T3 (==INT6) */
	63	OCR4B = TCNT4;
	64	TIFR4 = _BV(OCF4B); /* clear compare match flag */
	65	}
	66	while (ref_ovfl < 60) {
	67	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	68	if ((TIFR4 & _BV(OCF4B)) != 0) {
	69	TIFR4 = _BV(OCF4B);
	70	ref_ovfl++;
	71	}
	72	if ((TIFR3 & _BV(TOV3)) != 0) {
	73	TIFR3 = _BV(TOV3);
	74	x_ovfl++;
	75	}
	76	}
	77	}
	78
	79	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	80	EIFR = _BV(INTF6);
	81	for (;;) {
	82	if (EIFR & _BV(INTF6)) {
	83	TCCR3B = 0b000<<CS30; /* stop counter */
	84	ref_stop = TCNT4;
	85	break;
	86	}
	87	if ((TIFR4 & _BV(OCF4B)) != 0) {
	88	TIFR4 = _BV(OCF4B);
	89	ref_ovfl++;
	90	}
	91	}
	92	}
	93
	94	if ((TIFR3 & _BV(TOV3)) != 0) {
	95	TIFR3 = _BV(TOV3);
	96	x_ovfl++;
	97	}
	98
24ba732a L	99	uint32_t ref_cnt = (ref_stop - OCR4B) + ((uint32_t)ref_ovfl << 16);
	100	uint32_t x_cnt = TCNT3 + ((uint32_t) x_ovfl << 16);
	101	uint64_t x_tmp = (uint64_t) 100000 * (x_cnt * cycles);
	102
aea51b6c L	103	debug_cpu("TCNT3: %6u, ref_cnt: %9lu\n", TCNT3, ref_cnt);
aea51b6c L	104	debug_cpu("x_tmp: %lu %lu\n", (uint32_t) (x_tmp >> 32), (uint32_t) (x_tmp & 0xffffffff));
24ba732a L	105
	106	x_tmp = (x_tmp * getenv_ulong(PSTR(ENV_FMON), 10, F_CPU) + (ref_cnt / 2)) / ref_cnt;
	107
aea51b6c	108	debug_cpu("x_tmp: %lu %lu\n", (uint32_t) (x_tmp >> 32), (uint32_t) (x_tmp & 0xffffffff));
24ba732a L	109
	110	/* round to 5 decimal digits */
	111	int_fast8_t sc = 5;
aea51b6c	112	while (sc > 0 \|\| x_tmp >= 100000) {
24ba732a L	113	x_tmp = (x_tmp + 5)/10;
	114	sc--;
	115	}
	116	x_freq = x_tmp;
	117	while (sc < 0) {
	118	x_freq *= 10;
	119	sc++;
	120	}
24ba732a L	121
	122	/* Stop Timer */
	123	TCCR3B = 0;
	124	PRR1 \|= _BV(PRTIM3);
	125
	126	return x_freq;
	127	}
	128
aea51b6c L	129	static const FLASH uint8_t loop_code[] = {
	130	/* 0000 / 0x00, / nop */
	131	/* 0001 / 0xAF, / xor a */
	132	/* 0005 / 0xD3,0x32, / out (032h),a ;DCNTL */
	133	/* 0002 / 0xD3,0x36, / out (036h),a ;RCR */
	134	/* / / */
	135	/* 0006 / 0xD3,0x40, / out (040H),a ;Ready */
	136	/* / / */
	137	/* / / ;Z80 Z180(0W) Z180(MaxW) */
	138	/* 0008 / / loop: ;-------------------------- */
	139	/* 0008 / 0xDB,0x50, / in a,(050h) ;11 10 +33 19 /
	140	/* 000A / 0xC3,0x08,0x00 / jp loop ;10 9 +33 18 /
	141	/* ;-------------------------- */
	142	/* ;21 19 37 */
	143	};
24ba732a	144
aea51b6c L	145	command_ret_t do_cpu_freq(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char const argv[])
aea51b6c L	146	{
24ba732a	147
aea51b6c L	148	#define O_SILENT (1<<0)
	149	#define O_WENV (1<<1)
	150	#define O_LOAD_LOOP (1<<2)
	151	#define O_UNLOAD_LOOP (1<<3)
24ba732a	152
aea51b6c L	153	uint_fast8_t options = O_LOAD_LOOP \| O_UNLOAD_LOOP;
	154	uint_fast8_t lcycles = 19;
	155	uint16_t timeout = 1000;
	156	uint8_t eimsk_save;
24ba732a	157
aea51b6c	158	uint8_t mem_save[ARRAY_SIZE(loop_code)];
24ba732a	159
aea51b6c L	160	int opt;
	161	while ((opt = getopt(argc, argv, PSTR("swnuc:t:"))) != -1) {
	162	switch (opt) {
	163	case 's':
	164	options \|= O_SILENT;
	165	break;
	166	case 'w':
	167	options \|= O_WENV;
	168	break;
	169	case 'n':
	170	options &= ~O_LOAD_LOOP;
	171	break;
	172	case 'u':
	173	options &= ~O_UNLOAD_LOOP;
	174	break;
	175	case 'c':
	176	lcycles = eval_arg(optarg, NULL);
	177	break;
	178	case 't':
	179	timeout = eval_arg(optarg, NULL);
	180	break;
	181	default: /* '?' */
	182	return CMD_RET_USAGE;
24ba732a L	183	}
24ba732a L	184	}
aea51b6c L	185	if (argc - optind != 0)
aea51b6c L	186	return CMD_RET_USAGE;
24ba732a	187
aea51b6c L	188	if (z80_bus_state() & ZST_RUNNING) {
	189	if (!(options & O_SILENT))
	190	printf_P(PSTR("Frequency measuring failed. CPU allready running!\n"));
	191	return CMD_RET_FAILURE;
24ba732a L	192	}
	193
	194	ATOMIC_BLOCK(ATOMIC_FORCEON) {
aea51b6c	195	/* Save state and disable INT5/INT6 */
f6154a39 L	196	eimsk_save = EIMSK;
f6154a39 L	197	EIMSK &= ~_BV(INT6);
aea51b6c	198	EIMSK &= ~_BV(INT5);
f6154a39 L	199	}
f6154a39 L	200
aea51b6c L	201	z80_bus_cmd(Request);
	202	if (options & O_LOAD_LOOP) {
	203	z80_read_block(mem_save, 0, ARRAY_SIZE(loop_code));
	204	z80_write_block_P(loop_code, 0, ARRAY_SIZE(loop_code));
24ba732a	205	}
aea51b6c L	206	EIFR = _BV(INTF5); /* Reset pending int */
	207	z80_bus_cmd(Release);
	208	z80_bus_cmd(Run);
24ba732a	209
aea51b6c L	210	clear_ctrlc(); /* forget any previous Control C */
aea51b6c L	211	ERRNUM err = 0;
dbc1de70	212
aea51b6c L	213	/* Wait for falling edge */
	214	do {
	215	/* check for ctrl-c to abort... */
	216	if (had_ctrlc() \|\| ctrlc()) {
	217	err = EINTR;
	218	break;
dbc1de70	219	}
aea51b6c	220	} while ((EIFR & _BV(INTF5)) == 0);
dbc1de70	221
aea51b6c L	222	uint32_t cpu_freq = 0;
	223	if (!err)
	224	cpu_freq = z80_measure_phi(lcycles);
dbc1de70	225
aea51b6c L	226	z80_bus_cmd(Reset);
	227	if (options & O_UNLOAD_LOOP) {
	228	z80_bus_cmd(Request);
	229	z80_write_block(mem_save, 0, ARRAY_SIZE(loop_code));
	230	z80_bus_cmd(Release);
dbc1de70	231	}
f6154a39	232	ATOMIC_BLOCK(ATOMIC_FORCEON) {
aea51b6c L	233	/* Restore INT5/INT6 */
	234	if ((eimsk_save & _BV(INT5)) != 0)
	235	EIMSK \|= _BV(INT5);
f6154a39 L	236	if ((eimsk_save & _BV(INT6)) != 0)
	237	EIMSK \|= _BV(INT6);
	238	/* Reset pending int */
aea51b6c	239	EIFR = _BV(INTF5);
f6154a39 L	240	EIFR = _BV(INTF6);
	241	}
	242
aea51b6c L	243	Stat &= ~S_MSG_PENDING;
	244	Stat &= ~S_CON_PENDING;
	245
	246	if (err)
	247	cmd_error(CMD_RET_FAILURE, err, NULL);
	248
	249	if (!(options & O_SILENT)) {
	250	uint8_t sc = cpu_freq >> 28;
	251	printf_P(PSTR("%lu %3u\n"), cpu_freq & 0x0fffffff, sc);
	252	}
	253	#if 0
	254	if (options & O_WENV) {
	255	if (setenv_ulong(PSTR(ENV_CPU_FREQ), cpu_freq)) {
	256	if (!(options & O_SILENT))
	257	printf_P(PSTR("'SETENV (%S, %lu)' failed!\n"), PSTR(ENV_CPU_FREQ), cpu_freq);
	258	return CMD_RET_FAILURE;
	259	}
	260	}
24ba732a	261	#endif
aea51b6c L	262	return CMD_RET_SUCCESS;
aea51b6c L	263	}
dbc1de70	264
226d3221	265	static const FLASH char * const FLASH cpu_strings[] = {
aea51b6c	266	FSTR("Unknown"),
226d3221 L	267	FSTR("8080"),
	268	FSTR("8085"),
	269	FSTR("Z80"),
	270	FSTR("x180"),
	271	FSTR("HD64180"),
	272	FSTR("Z80180"),
	273	FSTR("Z80S180"),
	274	};
	275
	276	command_ret_t do_cpuchk(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char const argv[] UNUSED)
	277	{
f1e16f88	278	uint_fast8_t cputype = 0;
226d3221	279	ERRNUM err = ESUCCESS;
aea51b6c	280	uint8_t eimsk_save;
226d3221 L	281	uint8_t ram_save[cpuinfo_length];
	282
	283	if (z80_bus_state() & ZST_RUNNING) {
	284	err = ERUNNING;
	285	} else {
	286	z80_bus_request_or_exit();
	287	z80_read_block(ram_save, 0, cpuinfo_length);
	288	z80_load_mem(0, cpuinfo,
	289	&cpuinfo_sections,
	290	cpuinfo_address,
	291	cpuinfo_length_of_sections);
	292	z80_bus_cmd(Release);
	293
	294	if (argv[1] && (argv[1][0] == 'n'))
	295	goto donot;
	296
aea51b6c L	297	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	298	/* Save state and disable INT5/INT6 */
	299	eimsk_save = EIMSK;
	300	EIMSK &= ~_BV(INT6);
	301	EIMSK &= ~_BV(INT5);
	302	}
	303	EIFR = _BV(INTF5); /* Reset pending int */
226d3221 L	304	z80_bus_cmd(Run);
	305
	306	clear_ctrlc(); /* forget any previous Control C */
aea51b6c	307	do {
226d3221 L	308	/* check for ctrl-c to abort... */
	309	if (had_ctrlc() \|\| ctrlc()) {
	310	err = EINTR;
	311	break;
	312	}
aea51b6c	313	} while ((EIFR & _BV(INTF5)) == 0);
226d3221	314	z80_bus_cmd(Reset);
aea51b6c L	315	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	316	/* Restore INT5/INT6 */
	317	if ((eimsk_save & _BV(INT5)) != 0)
	318	EIMSK \|= _BV(INT5);
	319	if ((eimsk_save & _BV(INT6)) != 0)
	320	EIMSK \|= _BV(INT6);
	321	/* Reset pending int */
	322	EIFR = _BV(INTF5);
	323	EIFR = _BV(INTF6);
	324	}
	325	Stat &= ~S_MSG_PENDING;
	326	Stat &= ~S_CON_PENDING;
226d3221	327	z80_bus_cmd(Request);
aea51b6c L	328	if (z80_read(3) == 0xFF) {
	329	cputype = z80_read(4);
	330	}
	331	z80_write_block(ram_save, 0, cpuinfo_length);
226d3221 L	332	z80_bus_cmd(Release);
	333	}
	334
	335	donot:
	336
	337	if (err)
	338	cmd_error(CMD_RET_FAILURE, err, NULL);
	339
24ba732a L	340	if (cputype >= ARRAY_SIZE(cpu_strings))
	341	cputype = 0;
	342	printf_P(PSTR("Detected CPU: %S\n"), cpu_strings[cputype]);
226d3221 L	343
	344	return CMD_RET_SUCCESS;
	345	}
51dd0948	346
51dd0948 L	347	command_ret_t do_cpu_test(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char const argv[])
	348	{
	349
	350	uint32_t pulsewidth = 10; /* ms */
	351
51dd0948 L	352	int opt;
	353	while ((opt = getopt(argc, argv, PSTR("t:"))) != -1) {
	354	switch (opt) {
	355	case 't':
	356	pulsewidth = eval_arg(optarg, NULL);
	357	break;
	358	default: /* '?' */
	359	return CMD_RET_USAGE;
	360	}
	361	}
	362
	363	if ((z80_bus_state() & ZST_ACQUIRED) != RESET)
	364	cmd_error(CMD_RET_FAILURE, ERUNNING, NULL);
	365
	366	clear_ctrlc(); /* forget any previous Control C */
	367	do {
	368	z80_bus_cmd(Request);
	369	test_delay(pulsewidth);
	370	z80_bus_cmd(Release);
	371	test_delay(pulsewidth);
	372	} while (!(had_ctrlc() \|\| ctrlc()));
	373
	374	return CMD_RET_SUCCESS;
	375	}
	376
dbc1de70 L	377	command_ret_t do_bus_test(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char const argv[] UNUSED)
dbc1de70 L	378	{
f1e16f88	379	int ch;
dbc1de70 L	380
dbc1de70 L	381	#if 0
dbc1de70 L	382	int opt;
	383	while ((opt = getopt(argc, argv, PSTR("t:"))) != -1) {
	384	switch (opt) {
	385	case 't':
	386	pulsewidth = eval_arg(optarg, NULL);
	387	break;
	388	default: /* '?' */
	389	return CMD_RET_USAGE;
	390	}
	391	}
	392	#endif
	393
	394	my_puts_P(PSTR(
	395	" 1: RESET 4: RUN r: Toggle /RESET\n"
	396	" 2: REQUEST 5: RESTART b: Toggle /BUSREQ\n"
	397	" 3: RELEASE 6: M_CYCLE\n"
	398	"\n"
	399	//"Bus state: "
	400	));
	401
	402	do {
	403	ch = my_getchar(1);
	404	if (ch >= 0) {
	405	switch (ch) {
	406	case '1': /* bus_cmd RESET */
	407	case '2': /* bus_cmd REQUEST */
	408	case '3': /* bus_cmd RELEASE */
	409	case '4': /* bus_cmd RUN */
	410	case '5': /* bus_cmd RESTART */
	411	case '6': /* bus_cmd M_CYCLE */
	412	z80_bus_cmd(ch - '1' + Reset);
	413	break;
	414	case 'r': /* Toggle RESET */
	415	z80_toggle_reset();
	416	break;
	417	case 'b': /* Toggle BUSREQ */
	418	z80_toggle_busreq();
	419	break;
	420	}
	421	test_delay(10);
	422	uint32_t cycles = z80_get_busreq_cycles();
	423	printf_P(PSTR("\rState: %.2x, cycles: %lu, time: %luus "),
	424	z80_bus_state(), cycles, (uint32_t) (cycles * 1000000LL / F_CPU));
	425	}
	426	} while (ch != 0x03);
	427
	428	putchar('\n');
	429	return CMD_RET_SUCCESS;
	430	}
	431
d66348b4 L	432	command_ret_t do_busack_test(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char const argv[] UNUSED)
	433	{
	434
	435	if ((z80_bus_state() & ZST_ACQUIRED) != RESET)
	436	cmd_error(CMD_RET_FAILURE, ERUNNING, NULL);
	437
	438	z80_bus_cmd(Request);
	439	uint32_t result = z80_get_busreq_cycles();
	440	test_delay(20);
	441	z80_bus_cmd(Release);
	442
	443	#if 0
	444	long div;
	445
	446	pinconf = gpio_config_get(pin);
	447	if (pinconf == OUTPUT_TIMER) {
	448	div = gpio_clockdiv_get(pin);
dbc1de70	449	}
d66348b4 L	450	#endif
	451
	452
	453	printf_P(PSTR("cycles: %lu, time: %luus\n"), result, (uint32_t) (result * 1000000LL / F_CPU));
	454
	455	return CMD_RET_SUCCESS;
	456	}
	457
51dd0948 L	458
51dd0948 L	459	/*
aea51b6c	460	* command table for subcommands
51dd0948 L	461	*/
	462
	463	cmd_tbl_t cmd_tbl_cpu[] = {
	464	CMD_TBL_ITEM(
aea51b6c L	465	chkcpu, CONFIG_SYS_MAXARGS, CTBL_RPT\|CTBL_SUBCMDAUTO, do_cpuchk,
aea51b6c L	466	"Check/Identify CPU",
51dd0948 L	467	""
51dd0948 L	468	),
dbc1de70 L	469	CMD_TBL_ITEM(
	470	buscmd, CONFIG_SYS_MAXARGS, CTBL_RPT, do_bus_test,
	471	"Bus commands",
	472	""
	473	),
51dd0948 L	474	CMD_TBL_ITEM(
	475	test, CONFIG_SYS_MAXARGS, 1, do_cpu_test,
	476	"Do bus request/release cycles",
	477	"[-t pulsewidth]"
	478	),
d66348b4 L	479	CMD_TBL_ITEM(
	480	busack, 2, 1, do_busack_test,
	481	"Get time from /Reset high to /BUSACK low",
	482	""
	483	),
51dd0948 L	484	CMD_TBL_ITEM(
	485	freq, CONFIG_SYS_MAXARGS, 1, do_cpu_freq,
	486	"Measure cpu frequency",
dbc1de70 L	487	"[-qwn] [-c loopcycles] [-t timeout]\n"
	488	" -q Be quiet\n"
	489	// " -w Write result to environment variable '"ENV_CPU_FREQ"'"
51dd0948	490	),
dbc1de70	491
51dd0948 L	492	CMD_TBL_ITEM(
	493	help, CONFIG_SYS_MAXARGS, CTBL_RPT, do_help,
	494	"Print sub command description/usage",
	495	"\n"
	496	" - print brief description of all sub commands\n"
	497	"fat help command ...\n"
	498	" - print detailed usage of sub cmd 'command'"
	499	),
	500
	501	/* This does not use the CMD_TBL_ITEM macro as ? can't be used in symbol names */
	502	{FSTR("?"), CONFIG_SYS_MAXARGS, 1, do_help,
	503	NULL,
	504	#ifdef CONFIG_SYS_LONGHELP
	505	FSTR(""),
	506	#endif /* CONFIG_SYS_LONGHELP */
	507	NULL,
	508	#ifdef CONFIG_AUTO_COMPLETE
	509	NULL,
	510	#endif
	511	},
	512	/* Mark end of table */
	513	CMD_TBL_END(cmd_tbl_cpu)
	514	};
	515
	516
	517	command_ret_t do_cpu(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char const argv[] UNUSED)
	518	{
	519	//puts_P(PSTR("Huch?"));
	520
	521	return CMD_RET_USAGE;
	522	}
	523
	524
dbc1de70	525	#if 0 /* Z180 Single Step Functions */
51dd0948 L	526	/*
	527	* Z180 Single Step Functions
	528	*
	529	*/
	530
	531
	532	#define P_RUN PORTG
	533	#define RUN 1
	534	#define DDR_RUN DDRG
	535	#define P_STEP PORTG
	536	#define STEP 0
	537	#define DDR_STEP DDRG
	538	#define P_WAIT PORTG
	539	#define WAIT 2
	540	#define DDR_WAIT DDRG
	541	/* All three signals are on the same Port (PortG) */
	542	#define PORT_SS PORTG
	543	#define DDR_SS DDRG
	544	#define PIN_SS PING
	545
	546	static bool ss_available;
	547
	548	int single_step_setup(void)
	549	{
	550	ss_available = false;
	551
	552	#if 0
	553	if (z80_bus_state() & ZST_RUNNING \|\|
	554	!(z80_bus_cmd(Request) & ZST_ACQUIRED))
	555	return -1;
	556	#endif
	557
	558	/* STEP, RUN output, WAIT input */
	559
	560	PORT_SS \|= _BV(RUN) \| _BV(STEP);
	561	DDR_SS \|= _BV(RUN) \| _BV(STEP);
	562	DDR_SS &= ~_BV(WAIT);
	563
	564	/* RUN high, MREQ pulse --> WAIT should be low */
	565	z80_mreq_pulse();
	566
	567	if ((PIN_SS & _BV(WAIT)) == 0) {
	568
	569	/* RUN high, STEP pulse --> WAIT should be high */
	570	PIN_SS = _BV(STEP);
	571	PIN_SS = _BV(STEP);
	572	if ((PIN_SS & _BV(WAIT)) != 0) {
	573
	574	/* RUN high, MREQ pulse --> WAIT should be low */
	575	z80_mreq_pulse();
	576	if ((PIN_SS & _BV(WAIT)) == 0) {
	577
	578	/* RUN low --> WAIT should be high */
	579	PIN_SS = _BV(RUN);
	580	if ((PIN_SS & _BV(WAIT)) != 0) {
	581
	582	/* RUN low, STEP pulse --> WAIT should be high */
	583	PIN_SS = _BV(STEP);
	584	PIN_SS = _BV(STEP);
	585	if ((PIN_SS & _BV(WAIT)) != 0) {
	586
	587	/* all tests passed */
	588	ss_available = true;
	589	}
590	}
591	}
592	}
593	}
594
595	if (!ss_available) {
596	DDR_SS &= ~(_BV(STEP) \| _BV(RUN));
597	PORT_SS \|= _BV(RUN) \| _BV(STEP);
598	}
599
600	return ss_available ? 0 : -1;
601	}
602	#endif