Remove STM32 variant (and submodule libopencm3)

[z180-stamp.git] / z180 / asci1-i.180

	page	200\r
\r
\r
	extrn	buf.init\r
	extrn	isv_sw\r
\r
\r
	global	ser.init\r
	global	ser.ist,ser.in\r
	global	ser.ost,ser.out\r
\r
;TODO: define a trampoline area somewhere in top ram.\r
rtxisvjmp	equ	0FF60h	;momentan frei...\r
\r
	include config.inc\r
	include	z180reg.inc\r
\r
\r
;-----------------------------------------------------\r
\r
	dseg\r
\r
buf_start:\r
	mkbuf	s1.rx_id, ser1.inbuf, s1.rx_len\r
	mkbuf	s1.tx_id, ser1.outbuf, s1.tx_len\r
buf_end:\r
\r
\r
\r
;-----------------------------------------------------\r
\r
	cseg\r
;\r
; Init Serial I/O for console input and output (ASCI1)\r
;\r
\r
\r
ser.init:\r
;	ld	a,i\r
;	push	af		;save IFF\r
;	di\r
\r
	xor	a		;\r
	out0	(stat1),a	;Disable rx/tx interrupts\r
\r
	ld hl,rxtx_src		;move rx and tx isv to common ram\r
	ld de,rxtx_dst		;\r
	ld bc,rxtx_src_e-rxtx_src ;\r
	ldir			;\r
\r
	ld hl,rtxisvjmp		;rx/tx int vector\r
	ld (ivtab + IV$ASCI1),hl;\r
	ld a,0cdh		;\r
	ld (rtxisvjmp),a	;\r
	ld hl,isv_sw		;\r
	ld (rtxisvjmp + 1),hl	;\r
	ld hl,rxtxisv		;\r
	ld (rtxisvjmp + 3),hl	;\r
\r
; ASCI1: 8N1, highest baudrate (56700), CTS disabled\r
\r
	ld	a,M_MPBT\r
	out0	(cntlb1),a\r
	ld	a,M_RE + M_TE + M_MOD2\r
	out0	(cntla1),a\r
	ld	a,M_RIE\r
	out0	(stat1),a	;Enable rx interrupts\r
\r
	ld	ix,ser1.inbuf\r
	ld	a,ser1.inbuf.mask\r
	call	buf.init\r
	ld	ix,ser1.outbuf\r
	ld	a,ser1.outbuf.mask\r
	call	buf.init\r
\r
;	pop	af\r
;	ret	po\r
;	ei\r
	ret			;\r
\r
ser.ist:\r
	push	ix\r
	ld	ix,ser1.inbuf	;\r
\r
buf.empty:\r
	ld	a,(ix+o.in_idx)	;\r
	sub	(ix+o.out_idx)	;\r
	pop	ix\r
	ret	z\r
	or	0ffh\r
	ret\r
\r
ser.in:\r
	push	hl			;11\r
	push	de			;11\r
	ld	hl,ser1.inbuf-1		; 9	hl = &rx.out_idx\r
	ld	a,(hl)			; 6	a = rx.out_idx\r
	dec	hl			; 4	hl = &rx.in_idx\r
	jr	bg.w1\r
bg.wait:\r
	halt\r
bg.w1:\r
	cp	(hl)			; 6	while (out_idx==in_idx)\r
	jr	z,bg.wait		; 6 (/8)	;\r
\r
	ld	e,a			; 4\r
	ld	d,0			; 6\r
	inc	de\r
	inc	de\r
\r
	ex	de,hl			; 3\r
	add	hl,de			;10\r
	ld	l,(hl)			; 6\r
	ex	de,hl			; 3\r
\r
	inc	a			; 4\r
	dec	hl			; 4\r
	and	(hl)			; 6\r
	inc	hl			; 4\r
	inc	hl			; 4\r
	ld	(hl),a			; 7\r
\r
	ld	a,e			; 4\r
	pop	de			; 9\r
	pop	hl			; 9\r
	ret				; 9\r
					;   153\r
\r
ser.ost:\r
	push	ix\r
	ld	ix,ser1.outbuf		;\r
buf.full:\r
	ld	a,(ix+o.in_idx)		;\r
	inc	a\r
	and	(ix+o.mask)\r
	sub	(ix+o.out_idx)		;\r
	pop	ix\r
	ret	z\r
	or	0ffh\r
	ret\r
\r
\r
ser.out:\r
	push	ix\r
	ld	ix,ser1.outbuf		;\r
buf.put:\r
	push	hl			;\r
	push	bc\r
	push	ix\r
	pop	hl\r
	ld	a,c\r
	ld	c,(ix+o.in_idx)		;\r
	ld	b,0\r
	add	hl,bc\r
	ld	(hl),a\r
\r
	ld	a,c			;\r
	inc	a\r
	and	(ix+o.mask)\r
bp.wait:\r
	cp	(ix+o.out_idx)		;\r
	jr	z,bp.wait\r
	ld	(ix+o.in_idx),a\r
\r
	di			;036f\r
	in0	a,(stat1)	;0374\r
	set	TIE,a		;0377\r
	out0	(stat1),a	;0379\r
	ei			;037c\r
\r
	ld	a,b\r
	pop	bc\r
	pop	hl\r
	pop	ix\r
	ret\r
\r
\r
;------------------------------------------\r
; ASCI 1 Transmit/Receive interupt routines\r
; moved to common ram\r
\r
rxtx_src:\r
	dseg\r
rxtx_dst:				; (0c097h)  old\r
\r
rxtxisv:\r
	inidat\r
	in0 a,(stat1)			;receive flag set?\r
	jp p,txisv			;\r
\r
	in0	d,(rdr1)		;todo: break detection\r
	bit	FE,a			;framing error?\r
	jr	nz,??ri_1\r
\r
	push	ix\r
	ld	ix,ser1.inbuf		;\r
	ld	hl,ser1.inbuf		;\r
	ld	c,(ix+o.in_idx)		;\r
	ld	b,0\r
	add	hl,bc\r
\r
	ld	a,c			;\r
	inc	a\r
	and	(ix+o.mask)\r
	cp	(ix+o.out_idx)		;\r
	jr	z,??ri_0\r
	ld	(hl),d\r
	ld	(ix+o.in_idx),a\r
??ri_0:\r
	pop	ix\r
??ri_1:\r
	in0	a,(cntla1)		;0705	c0c0\r
	res	EFR,a			;0708\r
	out0	(cntla1),a		;070a\r
	ret\r
\r
	inidate\r
\r
txisv:\r
	inidat\r
	push	ix\r
	ld	ix,ser1.outbuf		;\r
\r
	ld	a,(ix+o.out_idx)	;\r
	cp	(ix+o.in_idx)		;\r
	jr	z,??ti_2\r
\r
	ld	hl,ser1.outbuf		;\r
	add	a,l\r
	ld	l,a\r
	jr	nc,??ti_1\r
	inc	h\r
??ti_1:\r
	ld	l,(hl)\r
	out0	(tdr1),l		;071b\r
\r
	ld	a,(ix+o.out_idx)	;\r
	inc	a\r
	and	(ix+o.mask)\r
	ld	(ix+o.out_idx),a\r
	jr	??ti_3\r
??ti_2:\r
	in0	a,(stat1)		;0730	disable tx-int\r
	res	TIE,a			;0733\r
	out0	(stat1),a		;0735\r
??ti_3:\r
	pop	ix\r
	ret\r
\r
	inidate\r
\r
	cseg\r
rxtx_src_e:\r
\r
\r
	end\r