workaround for bank/common border crossing problem. Initial multi sector transfer.

[z180-stamp.git] / z180 / config.inc

\r
FALSE	equ	0\r
TRUE	equ	NOT FALSE\r
\r
banked	equ	true\r
\r
;-----------------------------------------------------\r
; CPU and BANKING types\r
\r
\r
CPU_Z180	equ	TRUE\r
CPU_Z80		equ	FALSE\r
\r
ROMSYS		equ	FALSE\r
\r
AVRCLK		equ	18432		;[KHz]\r
\r
    if CPU_Z180\r
\r
;-----------------------------------------------------\r
FOSC		equ	AVRCLK/2	;Oscillator frequency [KHz]\r
PHI		equ	FOSC*2		;CPU frequency (clock doubler enabled)\r
\r
;-----------------------------------------------------\r
; Programmable Reload Timer (PRT)\r
\r
PRT_PRE		equ	20		;PRT prescaler\r
\r
; Reload value for 10 ms Int. (0.1KHz):\r
; tc10ms = phi/prescale/0.1KHz  = phi / (prescale/10)\r
\r
PRT_TC10MS	equ	PHI / (PRT_PRE/10)\r
\r
;-----------------------------------------------------\r
; MMU\r
\r
COMMON_SIZE	equ	16*1024		;Common Area size in bytes\r
					;must be multiple of 4K\r
\r
if (COMMON_SIZE mod 1000h)\r
	.printx COMMON_SIZE not multiple of 4K!\r
	end	;stop assembly\r
endif\r
\r
CSK	equ	COMMON_SIZE/1000h	;\r
CA	equ	10h - CSK		;common area start\r
BA	equ	0			;banked area start\r
\r
SYS$CBR		equ	0\r
SYS$CBAR	equ	CA*16 + CA	;CBAR in system mode\r
USR$CBAR	equ	CA*16 + BA	;CBAR in user mode (CP/M)\r
\r
\r
BANKS		equ	18		;max nr. of banks\r
\r
;-----------------------------------------------------\r
\r
CREFSH		equ	0		;Refresh rate register (disable refresh)\r
CWAITIO		equ	3 shl IWI0	;Max I/O Wait States, 0 Memory Wait States\r
PHI_X2		equ	0		;set to M_X2CM to enable the clock doubler\r
\r
    endif 		;CPU_Z180\r
    if	CPU_Z80\r
\r
PHI		equ	AVRCLK/5	;CPU frequency [KHz]\r
BAUDCLCK	equ	AVRCLK/10	;Baudrate clock [KHz]\r
;BDCLK16		equ\r
\r
SIOAD	EQU	0bch\r
SIOAC	EQU	0bdh\r
SIOBD	EQU	0beh\r
SIOBC	EQU	0bfh\r
\r
CTC0	EQU	0f4h\r
CTC1	EQU	0f5h\r
CTC2	EQU	0f6h\r
CTC3	EQU	0f7h\r
\r
;\r
; Init Serial I/O for console input and output (SIO-A)\r
;\r
; Baudrate clock: 1843200 Hz (Bus connector pin A17)\r
;\r
; Baudrate   Divider	SIO	CTC\r
; ---------------------------------\r
; 115200	  16	 16	  1\r
;  57600	  32	 16	  2\r
;  38400	  48	 16	  3\r
;  19200	  96	 16	  6\r
;   9600	 192	 16	 12\r
;   4800	 384	 16	 24\r
;   2400	 768	 16	 48\r
;   1200	1536	 16	 96\r
;    600	3072	 16	192\r
;    300	6144	 64	 92\r
\r
    endif	; CPU_Z80\r
\r
    if	ROMSYS\r
c$rom		equ	0a5h\r
ROM_EN		equ	0C0h\r
ROM_DIS		equ	ROMEN+1\r
     if CPU_Z180\r
CWAITROM 	equ	2 shl MWI0\r
     endif\r
    endif\r
\r
\r
DDTZRSTVEC 	equ	030h		;DDTZ Restart vector (breakpoints)\r
\r
INIDONE		equ	03Fh		;CP/M skip hw init, if this address\r
INIDONEVAL	equ	080h		;    is set to this value.\r
\r
mtx.fifo_len	equ	32		;Message transfer fifos\r
mtx.fifo_id	equ	0		;    This *must* have #0\r
mrx.fifo_len	equ	32\r
mrx.fifo_id	equ	1\r
\r
ci.fifo_len	equ	32		;AVRCON Character I/O via AVR\r
ci.fifo_id	equ	2\r
co.fifo_len	equ	32\r
co.fifo_id	equ	3\r
\r
s1.rx_len	equ	128		;Serial 1 (ASCI1) buffers\r
s1.rx_id	equ	4		;\r
s1.tx_len	equ	128		;\r
s1.tx_id	equ	5		;\r
\r
AVRINT5		equ	4Fh\r
AVRINT6		equ	5Fh\r
;PMSG		equ	80h\r
\r
;-----------------------------------------------------\r
; Definition of (logical) top 2 memory pages\r
\r
sysram_start	equ	0FE00h\r
stacksize	equ	80\r
\r
isvsw_loc	equ	0FEE0h\r
\r
ivtab		equ	0ffc0h		;int vector table\r
iv2tab		equ	ivtab + 2*9\r
\r
\r
\r
;-----------------------------------------------------\r
\r
o.id		equ	-4\r
o.mask		equ	-3\r
o.in_idx	equ	-2\r
o.out_idx	equ	-1\r
\r
	.lall\r
\r
mkbuf	macro	id,name,size\r
  if ((size AND (size-1)) NE 0) OR (size GT 256)\r
    .printx Error: buffer ^size must be power of 2 and in range 0..256!\r
    name&.mask equ ;wrong size error\r
  else\r
    db id\r
    ds 3\r
    name:: ds size\r
    name&.mask equ low (size-1)\r
    if size ne 0\r
      name&.end equ $-1\r
      name&.len equ size\r
      name&.id equ id\r
    endif\r
  endif\r
endm\r
\r
;-----------------------------------------------------\r
\r
inidat	macro\r
	cseg\r
??ps.a	defl	$\r
	endm\r
\r
inidate	macro\r
??ps.len defl	$ - ??ps.a\r
	dseg\r
	ds	??ps.len\r
	endm\r