[z180-stamp.git] / avr / cmd_cpu.c

/*
 * (C) Copyright 2018 Leo C. <erbl259-lmu@yahoo.de>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include "cmd_cpu.h"
//#include <ctype.h>
#include <util/atomic.h>

#include "z80-if.h"
#include "con-utils.h"
//#include "env.h"
#include "eval_arg.h"
#include "timer.h"
#include "getopt-min.h"
//#include "debug.h"

/* hack to get Z180 loadfile into flash memory */
#define const const FLASH
#include "../z180/cpuinfo.h"
#undef const


/*
 * delay for <count> ms...
 */
static void	test_delay(uint32_t count)
{
	uint32_t ts = get_timer(0);

	while (get_timer(ts) <= count);
}

static int32_t z80_measure_phi(uint8_t cycles, uint16_t wait_ms)
{
	uint16_t ref_stop;
	uint16_t ref_ovfl;
	uint32_t x_freq;
	uint8_t eimsk_save,eicrb_save;


	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		/* Save state and disable INT6 */
		eimsk_save = EIMSK;
		EIMSK &= ~_BV(INT6);
		/* Save state and set INT6 for falling edge */
		eicrb_save = EICRB;
		EICRB = (eicrb_save & ~(0b11 << ISC60)) | (0b10 << ISC60);
	}

	PRR1 &= ~_BV(PRTIM3);
	TCCR3A = 0;
	TCCR3B = 0b000<<CS30;	/* stop counter */
	TCNT3 = 0;
	TIFR3 = _BV(TOV3);
	ref_ovfl = 0;

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		/* Reset pending int */
		EIFR = _BV(INTF6);
		/* Wait for falling edge */
		while ((EIFR & _BV(INTF6)) == 0)
			;
		OCR4B = TCNT4;
		TCCR3B = 0b110<<CS30;	/* Count falling edges on T3 (==INT6) */
		TIFR4 = _BV(OCF4B);		/* clear compare match flag */
	}
	while (ref_ovfl < 60) {
		ATOMIC_BLOCK(ATOMIC_FORCEON) {
			if ((TIFR4 & _BV(OCF4B)) != 0) {
				TIFR4 = _BV(OCF4B);
				ref_ovfl++;
			}
		}
	}

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		EIFR = _BV(INTF6);
		for (;;) {
			if (EIFR & _BV(INTF6))
				break;
			if (TIFR4 & _BV(OCF4B)) {
				if (EIFR & _BV(INTF6))
					break;
				TIFR4 = _BV(OCF4B);
				if (EIFR & _BV(INTF6))
					break;
				ref_ovfl++;
				if (EIFR & _BV(INTF6))
					break;
				if (ref_ovfl == 0)
					break;
			}
		}
		ref_stop = TCNT4;
		TCCR3B = 0b000<<CS30;	/* stop counter */
		if ((TIFR4 & _BV(OCF4B)) != 0) {
			TIFR4 = _BV(OCF4B);
			if (ref_ovfl)
				ref_ovfl++;
		}
	}

	if (ref_ovfl == 0)
		x_freq = 0xFFFFFFFE;
	else
	{
		uint32_t ref_cnt = (ref_stop - OCR4B) + ((uint32_t)ref_ovfl << 16);

		x_freq = TCNT3;						/* x_cnt (17 bit) */
		if ((TIFR3 & _BV(TOV3)) != 0)
			x_freq += 1UL << 16;
		uint32_t x_cnt = x_freq;
		x_freq *= cycles;

		x_freq = ((uint64_t) x_freq * F_CPU + (ref_cnt / 2))/ ref_cnt;

		debug("ref_start: %6u, ref_stop: %6u, ref_ovfl: %4u, ref_cnt: %9lu\n"
					  "    TCNT3: %6u,    x_cnt: %6lu, cycles: %3u, xfreq: %9lu\n",
					OCR4B, ref_stop, ref_ovfl, ref_cnt,
					TCNT3, x_cnt, cycles, x_freq);

		/* round to 5 decimal digits */
		uint8_t sc = 0;
		while (x_freq >= 100000UL) {
			x_freq = (x_freq + 5)/10;
			++sc;
		}
		while (sc--)
			x_freq *= 10;
	}

	/* Stop Timer */
	TCCR3B = 0;
	PRR1 |= _BV(PRTIM3);

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		/* Restore INT6 */
#if 0 /* wtf? */
		eicrb_save = EICRB;
		EICRB = (EICRB & ~(0b11 << ISC60)) | (eicrb_save & (0b11 << ISC60));
#endif
		EICRB = eicrb_save;
		if ((eimsk_save & _BV(INT6)) != 0)
			EIMSK |= _BV(INT6);
		/* Reset pending int */
		EIFR = _BV(INTF6);
	}

	return (int32_t) x_freq;
}


static const FLASH char * const FLASH cpu_strings[] = {
	FSTR("Unknown CPU"),
	FSTR("8080"),
	FSTR("8085"),
	FSTR("Z80"),
	FSTR("x180"),
	FSTR("HD64180"),
	FSTR("Z80180"),
	FSTR("Z80S180"),
};

command_ret_t do_cpuchk(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char * const argv[] UNUSED)
{
	uint8_t done = 0;
	uint8_t cputype;
	ERRNUM err = ESUCCESS;
	uint8_t ram_save[cpuinfo_length];

	if (z80_bus_state() & ZST_RUNNING) {
		err = ERUNNING;
	} else {
		z80_bus_request_or_exit();
		z80_read_block(ram_save, 0, cpuinfo_length);
		z80_load_mem(0, cpuinfo,
					&cpuinfo_sections,
					cpuinfo_address,
					cpuinfo_length_of_sections);
		z80_bus_cmd(Release);

		if (argv[1] && (argv[1][0] == 'n'))
			goto donot;

		z80_bus_cmd(Run);

		clear_ctrlc();		/* forget any previous Control C */
		while (done != 0xFF) {
			_delay_ms(8);
			/* check for ctrl-c to abort... */
			if (had_ctrlc() || ctrlc()) {
				err = EINTR;
				break;
			}
			z80_bus_cmd(Request);
			done = z80_read(3);
			if (done == 0xFF)
				cputype = z80_read(4);
			z80_bus_cmd(Release);
		}
		z80_bus_cmd(Reset);
		z80_bus_cmd(Request);
//		z80_write_block(ram_save, 0, cpuinfo_length);
		z80_bus_cmd(Release);
	}

donot:

	if (err)
		cmd_error(CMD_RET_FAILURE, err, NULL);

	if (done == 0xFF) {
		if (cputype >= ARRAY_SIZE(cpu_strings))
			cputype = 0;
		printf_P(PSTR("Detected CPU: %S\n"), cpu_strings[cputype]);
	}

	return CMD_RET_SUCCESS;
}

command_ret_t do_cpu_test(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char * const argv[])
{

	uint32_t pulsewidth = 10; /* ms */

	/* reset getopt() */
	optind = 0;

	int opt;
	while ((opt = getopt(argc, argv, PSTR("t:"))) != -1) {
		switch (opt) {
		case 't':
			pulsewidth = eval_arg(optarg, NULL);
			break;
		default: /* '?' */
			return CMD_RET_USAGE;
		}
	}

	if ((z80_bus_state() & ZST_ACQUIRED) != RESET)
		cmd_error(CMD_RET_FAILURE, ERUNNING, NULL);

	clear_ctrlc();		/* forget any previous Control C */
	do {
		z80_bus_cmd(Request);
		test_delay(pulsewidth);
		z80_bus_cmd(Release);
		test_delay(pulsewidth);
	} while (!(had_ctrlc() || ctrlc()));

	return CMD_RET_SUCCESS;
}

command_ret_t do_bus_test(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char * const argv[] UNUSED)
{
	char ch;

#if 0
	/* reset getopt() */
	optind = 0;
	int opt;
	while ((opt = getopt(argc, argv, PSTR("t:"))) != -1) {
		switch (opt) {
		case 't':
			pulsewidth = eval_arg(optarg, NULL);
			break;
		default: /* '?' */
			return CMD_RET_USAGE;
		}
	}
#endif

	my_puts_P(PSTR(
		"  1:  RESET         4:  RUN           r:  Toggle /RESET\n"
		"  2:  REQUEST       5:  RESTART       b:  Toggle /BUSREQ\n"
		"  3:  RELEASE       6:  M_CYCLE\n"
		"\n"
		//"Bus state: "
	));

	do {
		ch = my_getchar(1);
		if (ch >= 0) {
			switch (ch) {
				case '1':		/* bus_cmd RESET   */
				case '2':		/* bus_cmd REQUEST */
				case '3':		/* bus_cmd RELEASE */
				case '4':		/* bus_cmd RUN     */
				case '5':		/* bus_cmd RESTART */
				case '6':		/* bus_cmd M_CYCLE */
						z80_bus_cmd(ch - '1' + Reset);
						break;
				case 'r':		/* Toggle RESET    */
						z80_toggle_reset();
						break;
				case 'b':		/* Toggle BUSREQ   */
						z80_toggle_busreq();
						break;
			}
			test_delay(10);
			uint32_t cycles = z80_get_busreq_cycles();
			printf_P(PSTR("\rState: %.2x, cycles: %lu, time: %luus      "),
					z80_bus_state(), cycles, (uint32_t) (cycles * 1000000LL / F_CPU));
		}
	} while (ch != 0x03);

	putchar('\n');
	return CMD_RET_SUCCESS;
}

command_ret_t do_busack_test(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char * const argv[] UNUSED)
{

	if ((z80_bus_state() & ZST_ACQUIRED) != RESET)
		cmd_error(CMD_RET_FAILURE, ERUNNING, NULL);

	z80_bus_cmd(Request);
	uint32_t result = z80_get_busreq_cycles();
	test_delay(20);
	z80_bus_cmd(Release);

#if 0
	long div;

	pinconf = gpio_config_get(pin);
	if (pinconf == OUTPUT_TIMER) {
		div = gpio_clockdiv_get(pin);
	}
#endif


	printf_P(PSTR("cycles: %lu, time: %luus\n"), result, (uint32_t) (result * 1000000LL / F_CPU));

	return CMD_RET_SUCCESS;
}

static const FLASH uint8_t loop_code[] = {
	/* 0000 */  0x01,0x36,0x00,		/* ld	bc,00*256+RCR                           */
	/* 0003 */  0xAF,	         	/* xor	a                                       */
	/* 0004 */  0xED,0x79,       	/* out	(c),a                                   */
	/* 0006 */  0xD3,0x40,       	/* out	(040H),a                                */
	/*      */  		         	/* 					;Z80	Z180(0W) Z180(MaxW) */
	/* 0008 */  		         	/* loop:			;-------------------------- */
	/* 0008 */  0xDB,0x50       	/* in	a,(050h)	;11       10     +3*3  19   */
	/* 000A */  0xC3,0x08,0x00     	/* jp	loop		;10	   	   9	 +3*3  18   */
									/* 					;-------------------------- */
									/* 					;21       19           37   */
}

command_ret_t do_cpu_freq(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char * const argv[])
{

#define O_SILENT		(1<<0)
#define O_WENV			(1<<1)
#define O_LOAD_LOOP     (1<<2)
#define O_UNLOAD_LOOP   (1<<3)

	uint_fast8_t options = O_LOAD_LOOP | O_UNLOAD_LOOP;
	uint8_t lcycles = 18;
	uint16_t timeout = 1000;

	uint8_t mem_save[ARRAY_SIZE(loop_code)];

	/* reset getopt() */
	optind = 0;

	int opt;
	while ((opt = getopt(argc, argv, PSTR("swnuc:t:"))) != -1) {
		switch (opt) {
		case 's':
			options |= O_SILENT;
			break;
		case 'w':
			options |= O_WENV;
			break;
		case 'n':
			options &= ~O_LOAD_LOOP;
			break;
		case 'u':
			options &= ~O_UNLOAD_LOOP;
			break;
		case 'c':
			lcycles = eval_arg(optarg, NULL);
			break;
		case 't':
			timeout = eval_arg(optarg, NULL);
			break;
		default: /* '?' */
			return CMD_RET_USAGE;
		}
	}
	if (argc - optind != 0)
		return CMD_RET_USAGE;

	if (z80_bus_state() & ZST_RUNNING) {
		if (!(options & O_SILENT))
			printf_P(PSTR("Frequency measuring failed. CPU allready running!\n"));
		return CMD_RET_FAILURE;
	}


	z80_bus_cmd(Request);
	if (options & O_LOAD_LOOP) {
		z80_read_block(mem_save, 0, ARRAY_SIZE(loop_code));
		z80_write_block_P(loop_code, 0, ARRAY_SIZE(loop_code));
	}
	Stat &= ~S_IO_0X40;				/* Reset pending int */
	z80_bus_cmd(Release);
	z80_bus_cmd(Run);

	clear_ctrlc();					/* forget any previous Control C */
	ERRNUM err = 0;

	/* Wait for falling edge */
	do {
		/* check for ctrl-c to abort... */
		if (had_ctrlc() || ctrlc()) {
			err = EINTR;
			break;
		}
	} while ((Stat & S_IO_0X40) == 0);

	int32_t cpu_freq;
	if (!err)
		cpu_freq = z80_measure_phi(lcycles, false, timeout);

	z80_bus_cmd(Reset);
	if (options & O_UNLOAD_LOOP) {
		z80_bus_cmd(Request);
		z80_write_block(mem_save, 0, ARRAY_SIZE(loop_code));
		z80_bus_cmd(Release);
	}
	if (err)
		cmd_error(CMD_RET_FAILURE, err, NULL);

	if (!(options & O_SILENT)) {
		printf_P(PSTR("%ld%S\n"), cpu_freq, cpu_freq < 0 ? PSTR("") : PSTR("Hz"));
//		if (cpu_freq != 0)
//		else
//			printf_P(PSTR("No CPU clock or input frequency to low!\n"));
	}
#if 0
	if (options & O_WENV) {
		if (setenv_ulong(PSTR(ENV_CPU_FREQ), cpu_freq)) {
			if (!(options & O_SILENT))
				printf_P(PSTR("'SETENV (%S, %lu)' failed!\n"), PSTR(ENV_CPU_FREQ), cpu_freq);
			return CMD_RET_FAILURE;
		}
	}
#endif
	return CMD_RET_SUCCESS;
}


/*
 * command table for fat subcommands
 */

cmd_tbl_t cmd_tbl_cpu[] = {
CMD_TBL_ITEM(
	chkcpu,	CONFIG_SYS_MAXARGS,	CTBL_RPT,	do_cpuchk,
	"Check CPU",
	""
),
CMD_TBL_ITEM(
	buscmd,	CONFIG_SYS_MAXARGS,	CTBL_RPT,	do_bus_test,
	"Bus commands",
	""
),
CMD_TBL_ITEM(
	test,	CONFIG_SYS_MAXARGS,	1,	do_cpu_test,
	"Do bus request/release cycles",
	"[-t pulsewidth]"
),
CMD_TBL_ITEM(
	busack,	2,	1,	do_busack_test,
	"Get time from /Reset high to /BUSACK low",
	""
),
CMD_TBL_ITEM(
	freq,	CONFIG_SYS_MAXARGS,	1,	do_cpu_freq,
	"Measure cpu frequency",
	"[-qwn] [-c loopcycles] [-t timeout]\n"
	"     -q Be quiet\n"
//	"     -w  Write result to environment variable '"ENV_CPU_FREQ"'"
),

CMD_TBL_ITEM(
	help,	CONFIG_SYS_MAXARGS,	CTBL_RPT,	do_help,
	"Print sub command description/usage",
	"\n"
	"       - print brief description of all sub commands\n"
	"fat help command ...\n"
	"       - print detailed usage of sub cmd 'command'"
),

/* This does not use the CMD_TBL_ITEM macro as ? can't be used in symbol names */
	{FSTR("?"),   CONFIG_SYS_MAXARGS, 1, do_help,
	 NULL,
#ifdef  CONFIG_SYS_LONGHELP
	FSTR(""),
#endif /* CONFIG_SYS_LONGHELP */
	NULL,
#ifdef CONFIG_AUTO_COMPLETE
	NULL,
#endif
},
/* Mark end of table */
CMD_TBL_END(cmd_tbl_cpu)
};


command_ret_t do_cpu(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char * const argv[] UNUSED)
{
	//puts_P(PSTR("Huch?"));

	return CMD_RET_USAGE;
}


#if 0		/* Z180 Single Step Functions */
/*
 * Z180 Single Step Functions
 *
 */


#define P_RUN		PORTG
#define RUN			1
#define DDR_RUN		DDRG
#define P_STEP		PORTG
#define STEP		0
#define DDR_STEP	DDRG
#define P_WAIT		PORTG
#define WAIT		2
#define DDR_WAIT	DDRG
/* All three signals are on the same Port (PortG) */
#define PORT_SS		PORTG
#define DDR_SS		DDRG
#define PIN_SS		PING

static bool ss_available;

int single_step_setup(void)
{
	ss_available = false;

#if 0
	if (z80_bus_state() & ZST_RUNNING ||
			!(z80_bus_cmd(Request) & ZST_ACQUIRED))
		return  -1;
#endif

	/* STEP, RUN output, WAIT input */

	PORT_SS |= _BV(RUN) | _BV(STEP);
	DDR_SS |= _BV(RUN) | _BV(STEP);
	DDR_SS &= ~_BV(WAIT);

	/* RUN high, MREQ pulse --> WAIT should be low */
	z80_mreq_pulse();

	if ((PIN_SS & _BV(WAIT)) == 0) {

		/* RUN high, STEP pulse --> WAIT should be high */
		PIN_SS = _BV(STEP);
		PIN_SS = _BV(STEP);
		if ((PIN_SS & _BV(WAIT)) != 0) {

			/* RUN high, MREQ pulse --> WAIT should be low */
			z80_mreq_pulse();
			if ((PIN_SS & _BV(WAIT)) == 0) {

				/* RUN low --> WAIT should be high */
				PIN_SS = _BV(RUN);
				if ((PIN_SS & _BV(WAIT)) != 0) {

					/* RUN low, STEP pulse --> WAIT should be high */
					PIN_SS = _BV(STEP);
					PIN_SS = _BV(STEP);
					if ((PIN_SS & _BV(WAIT)) != 0) {

						/* all tests passed */
						ss_available = true;
					}
				}
			}
		}
	}

	if (!ss_available) {
		DDR_SS &= ~(_BV(STEP) | _BV(RUN));
		PORT_SS |= _BV(RUN) | _BV(STEP);
	}

	return ss_available ? 0 : -1;
}
#endif
Commit	Line	Data
226d3221 L	1	/*
	2	* (C) Copyright 2018 Leo C. <erbl259-lmu@yahoo.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
	7	#include "cmd_cpu.h"
	8	//#include <ctype.h>
dbc1de70	9	#include <util/atomic.h>
226d3221 L	10
	11	#include "z80-if.h"
	12	#include "con-utils.h"
	13	//#include "env.h"
51dd0948 L	14	#include "eval_arg.h"
	15	#include "timer.h"
	16	#include "getopt-min.h"
226d3221 L	17	//#include "debug.h"
	18
	19	/* hack to get Z180 loadfile into flash memory */
	20	#define const const FLASH
	21	#include "../z180/cpuinfo.h"
	22	#undef const
	23
	24
dbc1de70 L	25	/*
	26	* delay for <count> ms...
	27	*/
	28	static void test_delay(uint32_t count)
	29	{
	30	uint32_t ts = get_timer(0);
	31
	32	while (get_timer(ts) <= count);
	33	}
	34
f6154a39	35	static int32_t z80_measure_phi(uint8_t cycles, uint16_t wait_ms)
dbc1de70 L	36	{
	37	uint16_t ref_stop;
	38	uint16_t ref_ovfl;
	39	uint32_t x_freq;
f6154a39	40	uint8_t eimsk_save,eicrb_save;
dbc1de70 L	41
dbc1de70 L	42
f6154a39 L	43	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	44	/* Save state and disable INT6 */
	45	eimsk_save = EIMSK;
	46	EIMSK &= ~_BV(INT6);
	47	/* Save state and set INT6 for falling edge */
	48	eicrb_save = EICRB;
	49	EICRB = (eicrb_save & ~(0b11 << ISC60)) \| (0b10 << ISC60);
	50	}
	51
dbc1de70 L	52	PRR1 &= ~_BV(PRTIM3);
	53	TCCR3A = 0;
	54	TCCR3B = 0b000<<CS30; /* stop counter */
	55	TCNT3 = 0;
	56	TIFR3 = _BV(TOV3);
	57	ref_ovfl = 0;
f6154a39	58
dbc1de70 L	59	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	60	/* Reset pending int */
	61	EIFR = _BV(INTF6);
	62	/* Wait for falling edge */
	63	while ((EIFR & _BV(INTF6)) == 0)
	64	;
dbc1de70 L	65	OCR4B = TCNT4;
	66	TCCR3B = 0b110<<CS30; /* Count falling edges on T3 (==INT6) */
	67	TIFR4 = _BV(OCF4B); /* clear compare match flag */
	68	}
	69	while (ref_ovfl < 60) {
	70	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	71	if ((TIFR4 & _BV(OCF4B)) != 0) {
	72	TIFR4 = _BV(OCF4B);
	73	ref_ovfl++;
	74	}
	75	}
	76	}
	77
	78	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	79	EIFR = _BV(INTF6);
	80	for (;;) {
	81	if (EIFR & _BV(INTF6))
	82	break;
	83	if (TIFR4 & _BV(OCF4B)) {
	84	if (EIFR & _BV(INTF6))
	85	break;
	86	TIFR4 = _BV(OCF4B);
	87	if (EIFR & _BV(INTF6))
	88	break;
	89	ref_ovfl++;
	90	if (EIFR & _BV(INTF6))
	91	break;
	92	if (ref_ovfl == 0)
	93	break;
	94	}
	95	}
	96	ref_stop = TCNT4;
	97	TCCR3B = 0b000<<CS30; /* stop counter */
	98	if ((TIFR4 & _BV(OCF4B)) != 0) {
	99	TIFR4 = _BV(OCF4B);
	100	if (ref_ovfl)
	101	ref_ovfl++;
	102	}
	103	}
	104
	105	if (ref_ovfl == 0)
	106	x_freq = 0xFFFFFFFE;
	107	else
	108	{
	109	uint32_t ref_cnt = (ref_stop - OCR4B) + ((uint32_t)ref_ovfl << 16);
	110
	111	x_freq = TCNT3; /* x_cnt (17 bit) */
	112	if ((TIFR3 & _BV(TOV3)) != 0)
	113	x_freq += 1UL << 16;
	114	uint32_t x_cnt = x_freq;
dbc1de70 L	115	x_freq *= cycles;
	116
	117	x_freq = ((uint64_t) x_freq * F_CPU + (ref_cnt / 2))/ ref_cnt;
	118
f6154a39 L	119	debug("ref_start: %6u, ref_stop: %6u, ref_ovfl: %4u, ref_cnt: %9lu\n"
f6154a39 L	120	" TCNT3: %6u, x_cnt: %6lu, cycles: %3u, xfreq: %9lu\n",
dbc1de70 L	121	OCR4B, ref_stop, ref_ovfl, ref_cnt,
	122	TCNT3, x_cnt, cycles, x_freq);
	123
	124	/* round to 5 decimal digits */
	125	uint8_t sc = 0;
	126	while (x_freq >= 100000UL) {
	127	x_freq = (x_freq + 5)/10;
	128	++sc;
	129	}
	130	while (sc--)
	131	x_freq *= 10;
	132	}
	133
	134	/* Stop Timer */
	135	TCCR3B = 0;
	136	PRR1 \|= _BV(PRTIM3);
	137
f6154a39 L	138	ATOMIC_BLOCK(ATOMIC_FORCEON) {
	139	/* Restore INT6 */
	140	#if 0 /* wtf? */
	141	eicrb_save = EICRB;
	142	EICRB = (EICRB & ~(0b11 << ISC60)) \| (eicrb_save & (0b11 << ISC60));
	143	#endif
	144	EICRB = eicrb_save;
	145	if ((eimsk_save & _BV(INT6)) != 0)
	146	EIMSK \|= _BV(INT6);
	147	/* Reset pending int */
	148	EIFR = _BV(INTF6);
	149	}
	150
dbc1de70 L	151	return (int32_t) x_freq;
	152	}
	153
	154
226d3221 L	155	static const FLASH char * const FLASH cpu_strings[] = {
	156	FSTR("Unknown CPU"),
	157	FSTR("8080"),
	158	FSTR("8085"),
	159	FSTR("Z80"),
	160	FSTR("x180"),
	161	FSTR("HD64180"),
	162	FSTR("Z80180"),
	163	FSTR("Z80S180"),
	164	};
	165
	166	command_ret_t do_cpuchk(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char const argv[] UNUSED)
	167	{
	168	uint8_t done = 0;
	169	uint8_t cputype;
	170	ERRNUM err = ESUCCESS;
	171	uint8_t ram_save[cpuinfo_length];
	172
	173	if (z80_bus_state() & ZST_RUNNING) {
	174	err = ERUNNING;
	175	} else {
	176	z80_bus_request_or_exit();
	177	z80_read_block(ram_save, 0, cpuinfo_length);
	178	z80_load_mem(0, cpuinfo,
	179	&cpuinfo_sections,
	180	cpuinfo_address,
	181	cpuinfo_length_of_sections);
	182	z80_bus_cmd(Release);
	183
	184	if (argv[1] && (argv[1][0] == 'n'))
	185	goto donot;
	186
	187	z80_bus_cmd(Run);
	188
	189	clear_ctrlc(); /* forget any previous Control C */
	190	while (done != 0xFF) {
	191	_delay_ms(8);
	192	/* check for ctrl-c to abort... */
	193	if (had_ctrlc() \|\| ctrlc()) {
	194	err = EINTR;
	195	break;
	196	}
	197	z80_bus_cmd(Request);
	198	done = z80_read(3);
	199	if (done == 0xFF)
	200	cputype = z80_read(4);
	201	z80_bus_cmd(Release);
	202	}
	203	z80_bus_cmd(Reset);
	204	z80_bus_cmd(Request);
	205	// z80_write_block(ram_save, 0, cpuinfo_length);
	206	z80_bus_cmd(Release);
	207	}
	208
	209	donot:
	210
	211	if (err)
	212	cmd_error(CMD_RET_FAILURE, err, NULL);
	213
	214	if (done == 0xFF) {
	215	if (cputype >= ARRAY_SIZE(cpu_strings))
	216	cputype = 0;
	217	printf_P(PSTR("Detected CPU: %S\n"), cpu_strings[cputype]);
	218	}
219
220	return CMD_RET_SUCCESS;
221	}
51dd0948	222
51dd0948 L	223	command_ret_t do_cpu_test(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char const argv[])
	224	{
	225
	226	uint32_t pulsewidth = 10; /* ms */
	227
	228	/* reset getopt() */
	229	optind = 0;
	230
	231	int opt;
	232	while ((opt = getopt(argc, argv, PSTR("t:"))) != -1) {
	233	switch (opt) {
	234	case 't':
	235	pulsewidth = eval_arg(optarg, NULL);
	236	break;
	237	default: /* '?' */
	238	return CMD_RET_USAGE;
	239	}
	240	}
	241
	242	if ((z80_bus_state() & ZST_ACQUIRED) != RESET)
	243	cmd_error(CMD_RET_FAILURE, ERUNNING, NULL);
	244
	245	clear_ctrlc(); /* forget any previous Control C */
	246	do {
	247	z80_bus_cmd(Request);
	248	test_delay(pulsewidth);
	249	z80_bus_cmd(Release);
	250	test_delay(pulsewidth);
	251	} while (!(had_ctrlc() \|\| ctrlc()));
	252
	253	return CMD_RET_SUCCESS;
	254	}
	255
dbc1de70 L	256	command_ret_t do_bus_test(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char const argv[] UNUSED)
	257	{
	258	char ch;
	259
	260	#if 0
	261	/* reset getopt() */
	262	optind = 0;
	263	int opt;
	264	while ((opt = getopt(argc, argv, PSTR("t:"))) != -1) {
	265	switch (opt) {
	266	case 't':
	267	pulsewidth = eval_arg(optarg, NULL);
	268	break;
	269	default: /* '?' */
	270	return CMD_RET_USAGE;
	271	}
	272	}
	273	#endif
	274
	275	my_puts_P(PSTR(
	276	" 1: RESET 4: RUN r: Toggle /RESET\n"
	277	" 2: REQUEST 5: RESTART b: Toggle /BUSREQ\n"
	278	" 3: RELEASE 6: M_CYCLE\n"
	279	"\n"
	280	//"Bus state: "
	281	));
	282
	283	do {
	284	ch = my_getchar(1);
	285	if (ch >= 0) {
	286	switch (ch) {
	287	case '1': /* bus_cmd RESET */
	288	case '2': /* bus_cmd REQUEST */
	289	case '3': /* bus_cmd RELEASE */
	290	case '4': /* bus_cmd RUN */
	291	case '5': /* bus_cmd RESTART */
	292	case '6': /* bus_cmd M_CYCLE */
	293	z80_bus_cmd(ch - '1' + Reset);
	294	break;
	295	case 'r': /* Toggle RESET */
	296	z80_toggle_reset();
	297	break;
	298	case 'b': /* Toggle BUSREQ */
	299	z80_toggle_busreq();
	300	break;
	301	}
	302	test_delay(10);
	303	uint32_t cycles = z80_get_busreq_cycles();
	304	printf_P(PSTR("\rState: %.2x, cycles: %lu, time: %luus "),
	305	z80_bus_state(), cycles, (uint32_t) (cycles * 1000000LL / F_CPU));
	306	}
	307	} while (ch != 0x03);
	308
	309	putchar('\n');
	310	return CMD_RET_SUCCESS;
	311	}
	312
d66348b4 L	313	command_ret_t do_busack_test(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char const argv[] UNUSED)
	314	{
	315
	316	if ((z80_bus_state() & ZST_ACQUIRED) != RESET)
	317	cmd_error(CMD_RET_FAILURE, ERUNNING, NULL);
	318
	319	z80_bus_cmd(Request);
	320	uint32_t result = z80_get_busreq_cycles();
	321	test_delay(20);
	322	z80_bus_cmd(Release);
	323
	324	#if 0
	325	long div;
	326
	327	pinconf = gpio_config_get(pin);
	328	if (pinconf == OUTPUT_TIMER) {
	329	div = gpio_clockdiv_get(pin);
dbc1de70	330	}
d66348b4 L	331	#endif
	332
	333
	334	printf_P(PSTR("cycles: %lu, time: %luus\n"), result, (uint32_t) (result * 1000000LL / F_CPU));
	335
	336	return CMD_RET_SUCCESS;
	337	}
	338
f6154a39 L	339	static const FLASH uint8_t loop_code[] = {
	340	/* 0000 / 0x01,0x36,0x00, / ld bc,00256+RCR /
	341	/* 0003 / 0xAF, / xor a */
	342	/* 0004 / 0xED,0x79, / out (c),a */
	343	/* 0006 / 0xD3,0x40, / out (040H),a */
	344	/* / / ;Z80 Z180(0W) Z180(MaxW) */
	345	/* 0008 / / loop: ;-------------------------- */
	346	/* 0008 / 0xDB,0x50 / in a,(050h) ;11 10 +33 19 /
	347	/* 000A / 0xC3,0x08,0x00 / jp loop ;10 9 +33 18 /
	348	/* ;-------------------------- */
	349	/* ;21 19 37 */
	350	}
	351
dbc1de70	352	command_ret_t do_cpu_freq(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char const argv[])
51dd0948	353	{
dbc1de70 L	354
	355	#define O_SILENT (1<<0)
	356	#define O_WENV (1<<1)
	357	#define O_LOAD_LOOP (1<<2)
	358	#define O_UNLOAD_LOOP (1<<3)
	359
	360	uint_fast8_t options = O_LOAD_LOOP \| O_UNLOAD_LOOP;
51dd0948 L	361	uint8_t lcycles = 18;
	362	uint16_t timeout = 1000;
	363
f6154a39	364	uint8_t mem_save[ARRAY_SIZE(loop_code)];
51dd0948 L	365
	366	/* reset getopt() */
	367	optind = 0;
	368
	369	int opt;
dbc1de70	370	while ((opt = getopt(argc, argv, PSTR("swnuc:t:"))) != -1) {
51dd0948 L	371	switch (opt) {
51dd0948 L	372	case 's':
dbc1de70	373	options \|= O_SILENT;
51dd0948 L	374	break;
51dd0948 L	375	case 'w':
dbc1de70	376	options \|= O_WENV;
51dd0948 L	377	break;
51dd0948 L	378	case 'n':
dbc1de70 L	379	options &= ~O_LOAD_LOOP;
	380	break;
	381	case 'u':
	382	options &= ~O_UNLOAD_LOOP;
51dd0948 L	383	break;
	384	case 'c':
	385	lcycles = eval_arg(optarg, NULL);
	386	break;
	387	case 't':
dbc1de70	388	timeout = eval_arg(optarg, NULL);
51dd0948 L	389	break;
	390	default: /* '?' */
	391	return CMD_RET_USAGE;
	392	}
	393	}
dbc1de70 L	394	if (argc - optind != 0)
dbc1de70 L	395	return CMD_RET_USAGE;
51dd0948 L	396
51dd0948 L	397	if (z80_bus_state() & ZST_RUNNING) {
dbc1de70	398	if (!(options & O_SILENT))
51dd0948 L	399	printf_P(PSTR("Frequency measuring failed. CPU allready running!\n"));
	400	return CMD_RET_FAILURE;
	401	}
	402
51dd0948 L	403
51dd0948 L	404	z80_bus_cmd(Request);
dbc1de70	405	if (options & O_LOAD_LOOP) {
f6154a39 L	406	z80_read_block(mem_save, 0, ARRAY_SIZE(loop_code));
f6154a39 L	407	z80_write_block_P(loop_code, 0, ARRAY_SIZE(loop_code));
51dd0948	408	}
dbc1de70	409	Stat &= ~S_IO_0X40; /* Reset pending int */
51dd0948	410	z80_bus_cmd(Release);
dbc1de70	411	z80_bus_cmd(Run);
51dd0948	412
dbc1de70 L	413	clear_ctrlc(); /* forget any previous Control C */
	414	ERRNUM err = 0;
	415
	416	/* Wait for falling edge */
	417	do {
	418	/* check for ctrl-c to abort... */
	419	if (had_ctrlc() \|\| ctrlc()) {
	420	err = EINTR;
	421	break;
	422	}
	423	} while ((Stat & S_IO_0X40) == 0);
	424
	425	int32_t cpu_freq;
	426	if (!err)
	427	cpu_freq = z80_measure_phi(lcycles, false, timeout);
51dd0948 L	428
51dd0948 L	429	z80_bus_cmd(Reset);
dbc1de70 L	430	if (options & O_UNLOAD_LOOP) {
dbc1de70 L	431	z80_bus_cmd(Request);
f6154a39	432	z80_write_block(mem_save, 0, ARRAY_SIZE(loop_code));
dbc1de70 L	433	z80_bus_cmd(Release);
dbc1de70 L	434	}
dbc1de70 L	435	if (err)
dbc1de70 L	436	cmd_error(CMD_RET_FAILURE, err, NULL);
51dd0948	437
dbc1de70 L	438	if (!(options & O_SILENT)) {
	439	printf_P(PSTR("%ld%S\n"), cpu_freq, cpu_freq < 0 ? PSTR("") : PSTR("Hz"));
	440	// if (cpu_freq != 0)
	441	// else
	442	// printf_P(PSTR("No CPU clock or input frequency to low!\n"));
	443	}
	444	#if 0
	445	if (options & O_WENV) {
51dd0948	446	if (setenv_ulong(PSTR(ENV_CPU_FREQ), cpu_freq)) {
dbc1de70	447	if (!(options & O_SILENT))
51dd0948 L	448	printf_P(PSTR("'SETENV (%S, %lu)' failed!\n"), PSTR(ENV_CPU_FREQ), cpu_freq);
	449	return CMD_RET_FAILURE;
	450	}
	451	}
dbc1de70	452	#endif
51dd0948 L	453	return CMD_RET_SUCCESS;
51dd0948 L	454	}
dbc1de70	455
51dd0948 L	456
	457	/*
	458	* command table for fat subcommands
	459	*/
	460
	461	cmd_tbl_t cmd_tbl_cpu[] = {
	462	CMD_TBL_ITEM(
	463	chkcpu, CONFIG_SYS_MAXARGS, CTBL_RPT, do_cpuchk,
	464	"Check CPU",
	465	""
	466	),
dbc1de70 L	467	CMD_TBL_ITEM(
	468	buscmd, CONFIG_SYS_MAXARGS, CTBL_RPT, do_bus_test,
	469	"Bus commands",
	470	""
	471	),
51dd0948 L	472	CMD_TBL_ITEM(
	473	test, CONFIG_SYS_MAXARGS, 1, do_cpu_test,
	474	"Do bus request/release cycles",
	475	"[-t pulsewidth]"
	476	),
d66348b4 L	477	CMD_TBL_ITEM(
	478	busack, 2, 1, do_busack_test,
	479	"Get time from /Reset high to /BUSACK low",
	480	""
	481	),
51dd0948 L	482	CMD_TBL_ITEM(
	483	freq, CONFIG_SYS_MAXARGS, 1, do_cpu_freq,
	484	"Measure cpu frequency",
dbc1de70 L	485	"[-qwn] [-c loopcycles] [-t timeout]\n"
	486	" -q Be quiet\n"
	487	// " -w Write result to environment variable '"ENV_CPU_FREQ"'"
51dd0948	488	),
dbc1de70	489
51dd0948 L	490	CMD_TBL_ITEM(
	491	help, CONFIG_SYS_MAXARGS, CTBL_RPT, do_help,
	492	"Print sub command description/usage",
	493	"\n"
	494	" - print brief description of all sub commands\n"
	495	"fat help command ...\n"
	496	" - print detailed usage of sub cmd 'command'"
	497	),
	498
	499	/* This does not use the CMD_TBL_ITEM macro as ? can't be used in symbol names */
	500	{FSTR("?"), CONFIG_SYS_MAXARGS, 1, do_help,
	501	NULL,
	502	#ifdef CONFIG_SYS_LONGHELP
	503	FSTR(""),
	504	#endif /* CONFIG_SYS_LONGHELP */
	505	NULL,
	506	#ifdef CONFIG_AUTO_COMPLETE
	507	NULL,
	508	#endif
	509	},
	510	/* Mark end of table */
	511	CMD_TBL_END(cmd_tbl_cpu)
	512	};
	513
	514
	515	command_ret_t do_cpu(cmd_tbl_t cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc UNUSED, char const argv[] UNUSED)
	516	{
	517	//puts_P(PSTR("Huch?"));
	518
	519	return CMD_RET_USAGE;
	520	}
	521
	522
dbc1de70	523	#if 0 /* Z180 Single Step Functions */
51dd0948 L	524	/*
	525	* Z180 Single Step Functions
	526	*
	527	*/
	528
	529
	530	#define P_RUN PORTG
	531	#define RUN 1
	532	#define DDR_RUN DDRG
	533	#define P_STEP PORTG
	534	#define STEP 0
	535	#define DDR_STEP DDRG
	536	#define P_WAIT PORTG
	537	#define WAIT 2
	538	#define DDR_WAIT DDRG
	539	/* All three signals are on the same Port (PortG) */
	540	#define PORT_SS PORTG
	541	#define DDR_SS DDRG
	542	#define PIN_SS PING
	543
	544	static bool ss_available;
	545
	546	int single_step_setup(void)
	547	{
	548	ss_available = false;
	549
	550	#if 0
	551	if (z80_bus_state() & ZST_RUNNING \|\|
	552	!(z80_bus_cmd(Request) & ZST_ACQUIRED))
	553	return -1;
	554	#endif
	555
	556	/* STEP, RUN output, WAIT input */
	557
	558	PORT_SS \|= _BV(RUN) \| _BV(STEP);
	559	DDR_SS \|= _BV(RUN) \| _BV(STEP);
	560	DDR_SS &= ~_BV(WAIT);
	561
	562	/* RUN high, MREQ pulse --> WAIT should be low */
	563	z80_mreq_pulse();
	564
	565	if ((PIN_SS & _BV(WAIT)) == 0) {
	566
	567	/* RUN high, STEP pulse --> WAIT should be high */
	568	PIN_SS = _BV(STEP);
	569	PIN_SS = _BV(STEP);
	570	if ((PIN_SS & _BV(WAIT)) != 0) {
	571
	572	/* RUN high, MREQ pulse --> WAIT should be low */
	573	z80_mreq_pulse();
	574	if ((PIN_SS & _BV(WAIT)) == 0) {
	575
	576	/* RUN low --> WAIT should be high */
	577	PIN_SS = _BV(RUN);
	578	if ((PIN_SS & _BV(WAIT)) != 0) {
	579
	580	/* RUN low, STEP pulse --> WAIT should be high */
	581	PIN_SS = _BV(STEP);
	582	PIN_SS = _BV(STEP);
	583	if ((PIN_SS & _BV(WAIT)) != 0) {
	584
	585	/* all tests passed */
	586	ss_available = true;
	587	}
588	}
589	}
590	}
591	}
592
593	if (!ss_available) {
594	DDR_SS &= ~(_BV(STEP) \| _BV(RUN));
595	PORT_SS \|= _BV(RUN) \| _BV(STEP);
596	}
597
598	return ss_available ? 0 : -1;
599	}
600	#endif