cleanup

[z180-stamp.git] / avr / z80-if.c

/**
 *
 * Pin assignments
 *
 * | Z180-Sig	|   AVR-Port	| Dir	|   Special Function	|
 * +------------+---------------+-------+-----------------------+
 * |	A0	| PA 	0	|  O	|			|
 * |	A1	| PA 	1	|  O	|			|
 * |	A2	| PA 	2	|  O	|			|
 * |	A3	| PA 	3	|  O	|			|
 * |	A4	| PA 	4	|  O	|			|
 * |	A5	| PA 	5	|  O	|			|
 * |	A6	| PA 	6	|  O	|			|
 * |	A7	| PA 	7	|  O	|			|
 * |	A8	| PC 	0	|  O	|			|
 * |	A9	| PC 	1	|  O	|			|
 * |	A10	| PC 	2	|  O	|			|
 * |	A11	| PC 	3	|  O	|			|
 * |	A12	| PC 	4	|  O	|			|
 * |	A13	| PC 	5	|  O	|			|
 * |	A14	| PC 	6	|  O	|			|
 * |	A15	| PC 	7	|  O	|			|
 * |	A16	| PE 	2	|  O	|			|
 * |	A17	| PE 	3	|  O	|			|
 * |	A18	| PE 	4	|  O	|			|
 * |	D0	| PF 	0	|  I/O	|			|
 * |	D1	| PF 	1	|  I/O	|			|
 * |	D2	| PF 	2	|  I/O	|			|
 * |	D3	| PF 	3	|  I/O	|			|
 * |	D4	| PF 	4	|  I/O	|			|
 * |	D5	| PF 	5	|  I/O	|			|
 * |	D6	| PF 	6	|  I/O	|			|
 * |	D7	| PF 	7	|  I/O	|			|
 * |	RD	| PD 	3	|  O	|			|
 * |	WR	| PD 	2	|  O	|			|
 * |	MREQ	| PD 	4	|  O	|			|
 * |	RST	| PD 	5	|  O	|			|
 * |	BUSREQ	| PD 	7	|  O	|			|
 * |	BUSACK	| PD 	6	|  I	|			|
 * |	IOCS1	| PE 	5	|  I	|			|
 * |*	HALT	| P 		|	|			|
 * |*	NMI	| P 		|	|			|
 * |		| P 		|  	|			|
 * |		| P 		|  	|  af1	 USART1_TX	|
 * |		| P 		|  	|  af1	 USART1_RX	|
 * |		| P 		|JTDI	|  remap SPI1_NSS'	|
 * |		| P 		|JTDO	|  remap SPI1_SCK'	|
 * |		| P 		|JTRST	|  remap SPI1_MISO'	|
 * |		| P 		|	|  remap SPI1_MOSI'	|
 * |		| P 		|	|  af1	 OSC32		|
 * |		| P 		|	|  af1	 OSC32		|


 */

#include <avr/io.h>
#include <util/atomic.h>
#include <stdio.h>
#include "debug.h"
#include "z80-if.h"


/* Number of array elements */
#define NELEMS(x)  (sizeof x/sizeof *x)

struct bits {
  uint8_t b0:1;
  uint8_t b1:1;
  uint8_t b2:1;
  uint8_t b3:1;
  uint8_t b4:1;
  uint8_t b5:1;
  uint8_t b6:1;
  uint8_t b7:1;
} __attribute__((__packed__));

typedef struct bits pbit_t;

#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)


//#define P_ZCLK		PORTB
//#define ZCLK		5
//#define DDR_ZCLK	DDRB
#define P_MREQ		PORTD
#define MREQ		4
#define DDR_MREQ	DDRD
#define P_RD		PORTD
#define RD		3
#define P_WR		PORTD
#define WR		2
#define P_BUSREQ	PORTD
#define BUSREQ		7
#define DDR_BUSREQ	DDRD
#define P_BUSACK	PORTD
#define PIN_BUSACK	PIND
#define BUSACK		6
#define DDR_BUSACK	DDRD
//#define P_HALT		PORTA
//#define HALT		12
#define P_IOCS1		PORTE
#define IOCS1		5
#define DDR_IOCS1		DDRE
//#define P_NMI		PORTB
//#define NMI		7
#define P_RST		PORTD
#define DDR_RST		DDRD
#define RST		5


#define P_DB		PORTF
#define PIN_DB		PINF
#define DDR_DB		DDRF

#define P_ADL		PORTA
#define P_ADH		PORTC
#define P_ADB		PORTE
#define PIN_ADB		PINE
#define DDR_ADL		DDRA
#define DDR_ADH		DDRC
#define DDR_ADB		DDRE

#define ADB_WIDTH	3
#define ADB_SHIFT	2
//#define ADB_PORT	PORTE


//#define Z80_O_ZCLK	SBIT(P_ZCLK, 5)
#define	Z80_O_MREQ	SBIT(P_MREQ, 4)
#define Z80_O_RD	SBIT(P_RD, 3)
#define Z80_O_WR	SBIT(P_WR, 2)
#define Z80_O_BUSREQ	SBIT(P_BUSREQ, 7)
//#define Z80_O_NMI	SBIT(P_NMI, )
#define Z80_O_RST	SBIT(P_RST, 5)
#define Z80_I_BUSACK	SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT	SBIT(P_HALT, )


#define MASK(n)	((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))


typedef union {
	uint32_t l;
	uint16_t w[2];
	uint8_t b[4];
} addr_t;


static zstate_t zstate;

/*--------------------------------------------------------------------------*/


static void z80_addrbus_set_tristate(void)
{
	/* /MREQ, /RD, /WR: Input, no pullup */
	DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
	Z80_O_MREQ = 0;
	Z80_O_RD = 0;
	Z80_O_WR = 0;

	P_ADL = 0;
	DDR_ADL = 0;
	P_ADH = 0;
	DDR_ADH = 0;
	PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_addrbus_set_active(void)
{
	/* /MREQ, /RD, /WR: Output and high */
	Z80_O_MREQ = 1;
	Z80_O_RD = 1;
	Z80_O_WR = 1;
	DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);

	DDR_ADL = 0xff;
	DDR_ADH = 0xff;
	DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_dbus_set_in(void)
{
	DDR_DB = 0;
	P_DB = 0;
}


static void z80_dbus_set_out(void)
{
	DDR_DB = 0xff;
}


static void z80_reset_pulse(void)
{
	Z80_O_RST = 0;
	_delay_us(10);
	Z80_O_RST = 1;
}


void z80_setup_bus(void)
{
	/* /ZRESET: Output and low */
	Z80_O_RST = 0;
	DDR_RST |= _BV(RST);

	/* /BUSREQ: Output and high */
	Z80_O_BUSREQ = 1;
	DDR_BUSREQ |= _BV(BUSREQ);

	/* /BUSACK: Input, no pullup */
	DDR_BUSACK &= ~_BV(BUSACK);
	P_BUSACK &= ~_BV(BUSACK);

	/* /IOCS1: Input, no pullup */
	DDR_IOCS1 &= ~_BV(IOCS1);
	P_IOCS1 &= ~_BV(IOCS1);

	z80_addrbus_set_tristate();
	z80_dbus_set_in();

	zstate = RESET;
}


zstate_t z80_bus_state(void)
{
	return zstate;
}


static void z80_busreq_hpulse(void)
{
	z80_dbus_set_in();
	z80_addrbus_set_tristate();

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		Z80_O_BUSREQ = 1;
		Z80_O_BUSREQ = 1;	/* 2 AVR clock cycles */
		Z80_O_BUSREQ = 0;	/* 2 AVR clock cycles */
	}

	if (zstate & ZST_ACQUIRED) {
		while(Z80_I_BUSACK == 1)
			;
		z80_addrbus_set_active();
	}
}


/*

 +              |		|		|		|		|
    +   State   |     RESET     |  RESET_AQRD   |    RUNNING    | RUNNING_AQRD  |
       +        |		|		|		|		|
          +     |	0	|	1	|	2	|	3	|
Event        +  |		|		|		|		|
----------------+---------------+---------------+---------------+---------------+
		|		|		|		|		|
Reset		|	0	|	0	|	0	|	0	|
		|		|		|		|		|
		|		|		|		|		|
Request		|	1	|		|	3	|		|
		|		|		|		|		|
		|		|		|		|		|
Release		|		|	0	|		|	2	|
		|		|		|		|		|
		|		|		|		|		|
Run		|	2	|	3	|		|		|
		|		|		|		|		|
		|		|		|		|		|
Restart		|		|		|	2	|	3	|
		|		|		|		|		|
		|		|		|		|		|
M_Cycle		|		|		|		|	3	|
		|		|		|		|		|
		|		|		|		|		|
*/

zstate_t z80_bus_cmd(bus_cmd_t cmd)
{
	switch (cmd) {

	case Reset:
		z80_dbus_set_in();
		z80_addrbus_set_tristate();
		Z80_O_RST = 0;
		Z80_O_BUSREQ = 1;
		zstate = RESET;
		break;

	case Request:
		switch (zstate) {
		case RESET:
			Z80_O_BUSREQ = 0;
			Z80_O_RST = 1;
			while(Z80_I_BUSACK == 1)
				;
			z80_addrbus_set_active();
			zstate = RESET_AQRD;
			break;

		case RUNNING:
			Z80_O_BUSREQ = 0;
			while(Z80_I_BUSACK == 1)
				;
			z80_addrbus_set_active();
			zstate = RUNNING_AQRD;
			break;

		default:
			break;
		}
		break;

	case Release:
		switch (zstate) {
		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_tristate();
			Z80_O_RST = 0;
			Z80_O_BUSREQ = 1;
			zstate = RESET;
			break;
		case RUNNING_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_tristate();
			Z80_O_BUSREQ = 1;
			zstate = RUNNING;
			break;
		default:
			break;
		}
		break;

	case Run:
		switch (zstate) {
		case RESET:
			Z80_O_RST = 1;
			zstate = RUNNING;
			break;

		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_tristate();
			z80_reset_pulse();
			z80_addrbus_set_active();
			zstate = RUNNING_AQRD;
			break;
		default:
			break;
		}
		break;

	case Restart:
		switch (zstate) {
		case RUNNING:
		case RUNNING_AQRD:
			z80_reset_pulse();
			break;
		default:
			break;
		}
		break;

	case M_Cycle:
		switch (zstate) {
		case RUNNING_AQRD:
			z80_busreq_hpulse();
			break;
		default:
			break;
		}
	}
	return zstate;
}


/*--------------------------------------------------------------------------*/

static
//inline __attribute__ ((always_inline))
void z80_setaddress(uint32_t addr)
{
	addr_t x; x.l = addr;

	P_ADL = x.b[0];
	P_ADH = x.b[1];
	PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
}

void z80_write(uint32_t addr, uint8_t data)
{
	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_out();
	P_DB = data;
	P_DB = data;
	Z80_O_WR = 0;
	Z80_O_WR = 0;
	Z80_O_WR = 1;
	Z80_O_MREQ = 1;
}

uint8_t z80_read(uint32_t addr)
{
	uint8_t data;

	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_in();
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	data = PIN_DB;
	Z80_O_RD = 1;
	Z80_O_MREQ = 1;

	return data;
}


void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
{
	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(addr++);
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
{
	uint8_t data;

	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(dest++);
		data = *src++;
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

/*
  0179'                         rx.bs_mask:	ds	1		; (buf_len - 1)
  017A'                         rx.in_idx:	ds	1		;
  017B'                         rx.out_idx:	ds	1		;
  017C'                         rx.buf:		ds	rx.buf_len	;
  018B'                         rx.buf_end	equ	$-1		; last byte (start+len-1)

  018C'                         tx.bs_mask:	ds	1		; (buf_len - 1)
  018D'                         tx.in_idx:	ds	1		;
  018E'                         tx.out_idx:	ds	1		;
  018F'                         tx.buf:		ds	tx.buf_len 	;
  019E'                         tx.buf_end	equ	$-1		; last byte
*/


typedef struct __attribute__((packed)) {
	uint8_t mask;
	uint8_t in_idx;
	uint8_t out_idx;
	uint8_t buf[];
} zfifo_t;



#define FIFO_BUFSIZE_MASK	-3
#define FIFO_INDEX_IN		-2
#define FIFO_INDEX_OUT		-1


static struct {
	uint32_t base;
	uint8_t idx_out,
		idx_in,
		mask;
	} fifo_dsc[NUM_FIFOS];


void z80_memfifo_init(const fifo_t f, uint32_t addr)
{
	fifo_dsc[f].base = addr;

	if (addr != 0) {

DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);

		z80_bus_cmd(Request);
		fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
		fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
		fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
		z80_bus_cmd(Release);
	}
}


int z80_memfifo_is_empty(const fifo_t f)
{
	int rc = 1;

	if (fifo_dsc[f].base != 0) {

		uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
		uint8_t idx;

		z80_bus_cmd(Request);
		idx = z80_read(adr);
		z80_bus_cmd(Release);
		rc = idx == fifo_dsc[f].idx_out;
	}

	return rc;
}

int z80_memfifo_is_full(const fifo_t f)
{
	int rc = 1;

	if (fifo_dsc[f].base != 0) {
		z80_bus_cmd(Request);
		rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
			== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
		z80_bus_cmd(Release);
	}
	return rc;
}


uint8_t z80_memfifo_getc_wait(const fifo_t f)
{
	uint8_t rc, idx;

	while (z80_memfifo_is_empty(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_out;
	rc = z80_read(fifo_dsc[f].base+idx);
	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
	z80_bus_cmd(Release);

	return rc;
}

int z80_memfifo_getc(const fifo_t f)
{
	int rc = -1;

	if (fifo_dsc[f].base != 0) {
		uint8_t idx = fifo_dsc[f].idx_out;
		z80_bus_cmd(Request);
		if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
			rc = z80_read(fifo_dsc[f].base+idx);
			fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
			z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
		}
		z80_bus_cmd(Release);
	}

	return rc;
}


void z80_memfifo_putc(fifo_t f, uint8_t val)
{
	int idx;

	while (z80_memfifo_is_full(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_in;
	z80_write(fifo_dsc[f].base+idx, val);
	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
	z80_bus_cmd(Release);
}