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Commit | Line | Data |
---|---|---|
1 | /** | |
2 | * | |
3 | * Pin assignments | |
4 | * | |
5 | * | Z180-Sig | AVR-Port | Dir | Special Function | | |
6 | * +------------+---------------+-------+-----------------------+ | |
7 | * | A0 | PA 0 | O | | | |
8 | * | A1 | PA 1 | O | | | |
9 | * | A2 | PA 2 | O | | | |
10 | * | A3 | PA 3 | O | | | |
11 | * | A4 | PA 4 | O | | | |
12 | * | A5 | PA 5 | O | | | |
13 | * | A6 | PA 6 | O | | | |
14 | * | A7 | PA 7 | O | | | |
15 | * | A8 | PC 0 | O | | | |
16 | * | A9 | PC 1 | O | | | |
17 | * | A10 | PC 2 | O | | | |
18 | * | A11 | PC 3 | O | | | |
19 | * | A12 | PC 4 | O | | | |
20 | * | A13 | PC 5 | O | | | |
21 | * | A14 | PC 6 | O | | | |
22 | * | A15 | PC 7 | O | | | |
23 | * | A16 | PE 2 | O | | | |
24 | * | A17 | PE 3 | O | | | |
25 | * | A18 | PE 4 | O | | | |
26 | * | D0 | PF 0 | I/O | | | |
27 | * | D1 | PF 1 | I/O | | | |
28 | * | D2 | PF 2 | I/O | | | |
29 | * | D3 | PF 3 | I/O | | | |
30 | * | D4 | PF 4 | I/O | | | |
31 | * | D5 | PF 5 | I/O | | | |
32 | * | D6 | PF 6 | I/O | | | |
33 | * | D7 | PF 7 | I/O | | | |
34 | * | RD | PD 3 | O | | | |
35 | * | WR | PD 2 | O | | | |
36 | * | MREQ | PD 4 | O | | | |
37 | * | RST | PD 5 | O | | | |
38 | * | BUSREQ | PD 7 | O | | | |
39 | * | BUSACK | PD 6 | I | | | |
40 | * | IOCS1 | PE 5 | I | | | |
41 | * |* HALT | P | | | | |
42 | * |* NMI | P | | | | |
43 | * | | P | | | | |
44 | * | | P | | af1 USART1_TX | | |
45 | * | | P | | af1 USART1_RX | | |
46 | * | | P |JTDI | remap SPI1_NSS' | | |
47 | * | | P |JTDO | remap SPI1_SCK' | | |
48 | * | | P |JTRST | remap SPI1_MISO' | | |
49 | * | | P | | remap SPI1_MOSI' | | |
50 | * | | P | | af1 OSC32 | | |
51 | * | | P | | af1 OSC32 | | |
52 | ||
53 | ||
54 | */ | |
55 | ||
56 | ||
57 | #include "common.h" | |
58 | #include <util/atomic.h> | |
59 | #include "debug.h" | |
60 | #include "z80-if.h" | |
61 | ||
62 | ||
63 | ||
64 | //#define P_ZCLK PORTB | |
65 | //#define ZCLK 5 | |
66 | //#define DDR_ZCLK DDRB | |
67 | #define P_MREQ PORTD | |
68 | #define MREQ 4 | |
69 | #define DDR_MREQ DDRD | |
70 | #define P_RD PORTD | |
71 | #define RD 3 | |
72 | #define P_WR PORTD | |
73 | #define WR 2 | |
74 | #define P_BUSREQ PORTD | |
75 | #define BUSREQ 7 | |
76 | #define DDR_BUSREQ DDRD | |
77 | #define P_BUSACK PORTD | |
78 | #define PIN_BUSACK PIND | |
79 | #define BUSACK 6 | |
80 | #define DDR_BUSACK DDRD | |
81 | //#define P_HALT PORTA | |
82 | //#define HALT 12 | |
83 | #define P_IOCS1 PORTE | |
84 | #define IOCS1 5 | |
85 | #define DDR_IOCS1 DDRE | |
86 | //#define P_NMI PORTB | |
87 | //#define NMI 7 | |
88 | #define P_RST PORTD | |
89 | #define DDR_RST DDRD | |
90 | #define RST 5 | |
91 | ||
92 | ||
93 | #define P_DB PORTF | |
94 | #define PIN_DB PINF | |
95 | #define DDR_DB DDRF | |
96 | ||
97 | #define P_ADL PORTA | |
98 | #define P_ADH PORTC | |
99 | #define P_ADB PORTE | |
100 | #define PIN_ADB PINE | |
101 | #define DDR_ADL DDRA | |
102 | #define DDR_ADH DDRC | |
103 | #define DDR_ADB DDRE | |
104 | ||
105 | #define ADB_WIDTH 3 | |
106 | #define ADB_SHIFT 2 | |
107 | //#define ADB_PORT PORTE | |
108 | ||
109 | ||
110 | //#define Z80_O_ZCLK SBIT(P_ZCLK, 5) | |
111 | #define Z80_O_MREQ SBIT(P_MREQ, 4) | |
112 | #define Z80_O_RD SBIT(P_RD, 3) | |
113 | #define Z80_O_WR SBIT(P_WR, 2) | |
114 | #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7) | |
115 | //#define Z80_O_NMI SBIT(P_NMI, ) | |
116 | #define Z80_O_RST SBIT(P_RST, 5) | |
117 | #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6) | |
118 | //#define Z80_I_HALT SBIT(P_HALT, ) | |
119 | ||
120 | ||
121 | #define BUS_TO 20 | |
122 | ||
123 | ||
124 | #define MASK(n) ((1<<(n))-1) | |
125 | #define SMASK(w,s) (MASK(w) << (s)) | |
126 | ||
127 | ||
128 | typedef union { | |
129 | uint32_t l; | |
130 | uint16_t w[2]; | |
131 | uint8_t b[4]; | |
132 | } addr_t; | |
133 | ||
134 | ||
135 | static zstate_t zstate; | |
136 | static volatile uint8_t timer; /* used for bus timeout */ | |
137 | ||
138 | /*---------------------------------------------------------*/ | |
139 | /* 10Hz timer interrupt generated by OC4A */ | |
140 | /*---------------------------------------------------------*/ | |
141 | ||
142 | ISR(TIMER4_COMPA_vect) | |
143 | { | |
144 | ||
145 | uint8_t i = timer; | |
146 | ||
147 | if (i) | |
148 | timer = i - 1; | |
149 | } | |
150 | ||
151 | /*--------------------------------------------------------------------------*/ | |
152 | ||
153 | ||
154 | static void z80_addrbus_set_tristate(void) | |
155 | { | |
156 | /* /MREQ, /RD, /WR: Input, no pullup */ | |
157 | DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR)); | |
158 | Z80_O_MREQ = 0; | |
159 | Z80_O_RD = 0; | |
160 | Z80_O_WR = 0; | |
161 | ||
162 | P_ADL = 0; | |
163 | DDR_ADL = 0; | |
164 | P_ADH = 0; | |
165 | DDR_ADH = 0; | |
166 | PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); | |
167 | DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); | |
168 | } | |
169 | ||
170 | ||
171 | static void z80_addrbus_set_active(void) | |
172 | { | |
173 | /* /MREQ, /RD, /WR: Output and high */ | |
174 | Z80_O_MREQ = 1; | |
175 | Z80_O_RD = 1; | |
176 | Z80_O_WR = 1; | |
177 | DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR); | |
178 | ||
179 | DDR_ADL = 0xff; | |
180 | DDR_ADH = 0xff; | |
181 | DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT); | |
182 | } | |
183 | ||
184 | ||
185 | static void z80_dbus_set_in(void) | |
186 | { | |
187 | DDR_DB = 0; | |
188 | P_DB = 0; | |
189 | } | |
190 | ||
191 | ||
192 | static void z80_dbus_set_out(void) | |
193 | { | |
194 | DDR_DB = 0xff; | |
195 | } | |
196 | ||
197 | ||
198 | static void z80_reset_pulse(void) | |
199 | { | |
200 | Z80_O_RST = 0; | |
201 | _delay_us(10); | |
202 | Z80_O_RST = 1; | |
203 | } | |
204 | ||
205 | ||
206 | void z80_setup_bus(void) | |
207 | { | |
208 | /* /ZRESET: Output and low */ | |
209 | Z80_O_RST = 0; | |
210 | DDR_RST |= _BV(RST); | |
211 | ||
212 | /* /BUSREQ: Output and high */ | |
213 | Z80_O_BUSREQ = 1; | |
214 | DDR_BUSREQ |= _BV(BUSREQ); | |
215 | ||
216 | /* /BUSACK: Input, no pullup */ | |
217 | DDR_BUSACK &= ~_BV(BUSACK); | |
218 | P_BUSACK &= ~_BV(BUSACK); | |
219 | ||
220 | /* /IOCS1: Input, no pullup */ | |
221 | DDR_IOCS1 &= ~_BV(IOCS1); | |
222 | P_IOCS1 &= ~_BV(IOCS1); | |
223 | ||
224 | z80_addrbus_set_tristate(); | |
225 | z80_dbus_set_in(); | |
226 | ||
227 | zstate = RESET; | |
228 | ||
229 | /* Timer 4 */ | |
230 | PRR1 &= ~_BV(PRTIM4); | |
231 | OCR4A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */ | |
232 | TCCR4B = (0b01<<WGM42)|(0b101<<CS30); /* CTC Mode, Prescaler 1024 */ | |
233 | TIMSK4 = _BV(OCIE4A); /* Enable oca interrupt */ | |
234 | ||
235 | } | |
236 | ||
237 | ||
238 | zstate_t z80_bus_state(void) | |
239 | { | |
240 | return zstate; | |
241 | } | |
242 | ||
243 | ||
244 | static void z80_busreq_hpulse(void) | |
245 | { | |
246 | z80_dbus_set_in(); | |
247 | z80_addrbus_set_tristate(); | |
248 | ||
249 | ATOMIC_BLOCK(ATOMIC_FORCEON) { | |
250 | Z80_O_BUSREQ = 1; | |
251 | Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */ | |
252 | Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */ | |
253 | } | |
254 | ||
255 | if (zstate & ZST_ACQUIRED) { | |
256 | timer = BUS_TO; | |
257 | while (Z80_I_BUSACK == 1 && timer) | |
258 | ; | |
259 | if (Z80_I_BUSACK == 0) | |
260 | z80_addrbus_set_active(); | |
261 | } | |
262 | } | |
263 | ||
264 | ||
265 | /* | |
266 | ||
267 | + | | | | | | |
268 | + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD | | |
269 | + | | | | | | |
270 | + | 0 | 1 | 2 | 3 | | |
271 | Event + | | | | | | |
272 | ----------------+---------------+---------------+---------------+---------------+ | |
273 | | | | | | | |
274 | Reset | 0 | 0 | 0 | 0 | | |
275 | | | | | | | |
276 | | | | | | | |
277 | Request | 1 | | 3 | | | |
278 | | | | | | | |
279 | | | | | | | |
280 | Release | | 0 | | 2 | | |
281 | | | | | | | |
282 | | | | | | | |
283 | Run | 2 | 3 | | | | |
284 | | | | | | | |
285 | | | | | | | |
286 | Restart | | | 2 | 3 | | |
287 | | | | | | | |
288 | | | | | | | |
289 | M_Cycle | | | | 3 | | |
290 | | | | | | | |
291 | | | | | | | |
292 | */ | |
293 | ||
294 | zstate_t z80_bus_cmd(bus_cmd_t cmd) | |
295 | { | |
296 | switch (cmd) { | |
297 | ||
298 | case Reset: | |
299 | z80_dbus_set_in(); | |
300 | z80_addrbus_set_tristate(); | |
301 | Z80_O_RST = 0; | |
302 | Z80_O_BUSREQ = 1; | |
303 | zstate = RESET; | |
304 | break; | |
305 | ||
306 | case Request: | |
307 | switch (zstate) { | |
308 | case RESET: | |
309 | Z80_O_BUSREQ = 0; | |
310 | Z80_O_RST = 1; | |
311 | timer = BUS_TO; | |
312 | while (Z80_I_BUSACK == 1 && timer) | |
313 | ; | |
314 | if (Z80_I_BUSACK == 0) { | |
315 | z80_addrbus_set_active(); | |
316 | zstate = RESET_AQRD; | |
317 | } else { | |
318 | Z80_O_RST = 0; | |
319 | Z80_O_BUSREQ = 1; | |
320 | } | |
321 | break; | |
322 | ||
323 | case RUNNING: | |
324 | Z80_O_BUSREQ = 0; | |
325 | timer = BUS_TO; | |
326 | while (Z80_I_BUSACK == 1 && timer) | |
327 | ; | |
328 | if (Z80_I_BUSACK == 0) { | |
329 | z80_addrbus_set_active(); | |
330 | zstate = RUNNING_AQRD; | |
331 | } else { | |
332 | Z80_O_BUSREQ = 1; | |
333 | } | |
334 | break; | |
335 | ||
336 | default: | |
337 | break; | |
338 | } | |
339 | break; | |
340 | ||
341 | case Release: | |
342 | switch (zstate) { | |
343 | case RESET_AQRD: | |
344 | z80_dbus_set_in(); | |
345 | z80_addrbus_set_tristate(); | |
346 | Z80_O_RST = 0; | |
347 | Z80_O_BUSREQ = 1; | |
348 | zstate = RESET; | |
349 | break; | |
350 | case RUNNING_AQRD: | |
351 | z80_dbus_set_in(); | |
352 | z80_addrbus_set_tristate(); | |
353 | Z80_O_BUSREQ = 1; | |
354 | zstate = RUNNING; | |
355 | break; | |
356 | default: | |
357 | break; | |
358 | } | |
359 | break; | |
360 | ||
361 | case Run: | |
362 | switch (zstate) { | |
363 | case RESET: | |
364 | Z80_O_RST = 1; | |
365 | zstate = RUNNING; | |
366 | break; | |
367 | ||
368 | case RESET_AQRD: | |
369 | z80_dbus_set_in(); | |
370 | z80_addrbus_set_tristate(); | |
371 | z80_reset_pulse(); | |
372 | z80_addrbus_set_active(); | |
373 | zstate = RUNNING_AQRD; | |
374 | break; | |
375 | default: | |
376 | break; | |
377 | } | |
378 | break; | |
379 | ||
380 | case Restart: | |
381 | switch (zstate) { | |
382 | case RUNNING: | |
383 | case RUNNING_AQRD: | |
384 | z80_reset_pulse(); | |
385 | break; | |
386 | default: | |
387 | break; | |
388 | } | |
389 | break; | |
390 | ||
391 | case M_Cycle: | |
392 | switch (zstate) { | |
393 | case RUNNING_AQRD: | |
394 | z80_busreq_hpulse(); /* TODO: */ | |
395 | break; | |
396 | default: | |
397 | break; | |
398 | } | |
399 | } | |
400 | return zstate; | |
401 | } | |
402 | ||
403 | ||
404 | /*--------------------------------------------------------------------------*/ | |
405 | ||
406 | static | |
407 | //inline __attribute__ ((always_inline)) | |
408 | void z80_setaddress(uint32_t addr) | |
409 | { | |
410 | addr_t x; x.l = addr; | |
411 | ||
412 | P_ADL = x.b[0]; | |
413 | P_ADH = x.b[1]; | |
414 | PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ; | |
415 | } | |
416 | ||
417 | void z80_write(uint32_t addr, uint8_t data) | |
418 | { | |
419 | z80_setaddress(addr); | |
420 | Z80_O_MREQ = 0; | |
421 | z80_dbus_set_out(); | |
422 | P_DB = data; | |
423 | P_DB = data; | |
424 | Z80_O_WR = 0; | |
425 | Z80_O_WR = 0; | |
426 | Z80_O_WR = 1; | |
427 | Z80_O_MREQ = 1; | |
428 | } | |
429 | ||
430 | uint8_t z80_read(uint32_t addr) | |
431 | { | |
432 | uint8_t data; | |
433 | ||
434 | z80_setaddress(addr); | |
435 | Z80_O_MREQ = 0; | |
436 | z80_dbus_set_in(); | |
437 | Z80_O_RD = 0; | |
438 | Z80_O_RD = 0; | |
439 | Z80_O_RD = 0; | |
440 | data = PIN_DB; | |
441 | Z80_O_RD = 1; | |
442 | Z80_O_MREQ = 1; | |
443 | ||
444 | return data; | |
445 | } | |
446 | ||
447 | ||
448 | void z80_memset(uint32_t addr, uint8_t data, uint32_t length) | |
449 | { | |
450 | z80_dbus_set_out(); | |
451 | Z80_O_MREQ = 0; | |
452 | P_DB = data; | |
453 | while(length--) { | |
454 | z80_setaddress(addr++); | |
455 | Z80_O_WR = 0; | |
456 | Z80_O_WR = 0; | |
457 | Z80_O_WR = 1; | |
458 | } | |
459 | Z80_O_MREQ = 1; | |
460 | } | |
461 | ||
462 | void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length) | |
463 | { | |
464 | uint8_t data; | |
465 | ||
466 | z80_dbus_set_out(); | |
467 | Z80_O_MREQ = 0; | |
468 | while(length--) { | |
469 | z80_setaddress(dest++); | |
470 | data = *src++; | |
471 | P_DB = data; | |
472 | P_DB = data; | |
473 | Z80_O_WR = 0; | |
474 | Z80_O_WR = 0; | |
475 | Z80_O_WR = 1; | |
476 | } | |
477 | Z80_O_MREQ = 1; | |
478 | } | |
479 | ||
480 | void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length) | |
481 | { | |
482 | uint8_t data; | |
483 | ||
484 | z80_dbus_set_out(); | |
485 | Z80_O_MREQ = 0; | |
486 | while(length--) { | |
487 | z80_setaddress(dest++); | |
488 | data = *src++; | |
489 | P_DB = data; | |
490 | P_DB = data; | |
491 | Z80_O_WR = 0; | |
492 | Z80_O_WR = 0; | |
493 | Z80_O_WR = 1; | |
494 | } | |
495 | Z80_O_MREQ = 1; | |
496 | } | |
497 | ||
498 | void z80_read_block (uint8_t *dest, uint32_t src, size_t length) | |
499 | { | |
500 | uint8_t data; | |
501 | ||
502 | Z80_O_MREQ = 0; | |
503 | z80_dbus_set_in(); | |
504 | while(length--) { | |
505 | z80_setaddress(src++); | |
506 | Z80_O_RD = 0; | |
507 | Z80_O_RD = 0; | |
508 | Z80_O_RD = 0; | |
509 | data = PIN_DB; | |
510 | Z80_O_RD = 1; | |
511 | *dest++ = data; | |
512 | } | |
513 | Z80_O_MREQ = 1; | |
514 | } | |
515 | ||
516 | ||
517 | /* | |
518 | 0179' rx.bs_mask: ds 1 ; (buf_len - 1) | |
519 | 017A' rx.in_idx: ds 1 ; | |
520 | 017B' rx.out_idx: ds 1 ; | |
521 | 017C' rx.buf: ds rx.buf_len ; | |
522 | 018B' rx.buf_end equ $-1 ; last byte (start+len-1) | |
523 | ||
524 | 018C' tx.bs_mask: ds 1 ; (buf_len - 1) | |
525 | 018D' tx.in_idx: ds 1 ; | |
526 | 018E' tx.out_idx: ds 1 ; | |
527 | 018F' tx.buf: ds tx.buf_len ; | |
528 | 019E' tx.buf_end equ $-1 ; last byte | |
529 | */ | |
530 | ||
531 | ||
532 | typedef struct __attribute__((packed)) { | |
533 | uint8_t mask; | |
534 | uint8_t in_idx; | |
535 | uint8_t out_idx; | |
536 | uint8_t buf[]; | |
537 | } zfifo_t; | |
538 | ||
539 | ||
540 | ||
541 | #define FIFO_BUFSIZE_MASK -3 | |
542 | #define FIFO_INDEX_IN -2 | |
543 | #define FIFO_INDEX_OUT -1 | |
544 | ||
545 | ||
546 | static struct { | |
547 | uint32_t base; | |
548 | uint8_t idx_out, | |
549 | idx_in, | |
550 | mask; | |
551 | } fifo_dsc[NUM_FIFOS]; | |
552 | ||
553 | ||
554 | void z80_memfifo_init(const fifo_t f, uint32_t addr) | |
555 | { | |
556 | fifo_dsc[f].base = addr; | |
557 | ||
558 | if (addr != 0) { | |
559 | ||
560 | DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr); | |
561 | ||
562 | z80_bus_cmd(Request); | |
563 | fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK); | |
564 | fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN); | |
565 | fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT); | |
566 | z80_bus_cmd(Release); | |
567 | } | |
568 | } | |
569 | ||
570 | ||
571 | int z80_memfifo_is_empty(const fifo_t f) | |
572 | { | |
573 | int rc = 1; | |
574 | ||
575 | if (fifo_dsc[f].base != 0) { | |
576 | ||
577 | uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN; | |
578 | uint8_t idx; | |
579 | ||
580 | z80_bus_cmd(Request); | |
581 | idx = z80_read(adr); | |
582 | z80_bus_cmd(Release); | |
583 | rc = idx == fifo_dsc[f].idx_out; | |
584 | } | |
585 | ||
586 | return rc; | |
587 | } | |
588 | ||
589 | int z80_memfifo_is_full(const fifo_t f) | |
590 | { | |
591 | int rc = 1; | |
592 | ||
593 | if (fifo_dsc[f].base != 0) { | |
594 | z80_bus_cmd(Request); | |
595 | rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask) | |
596 | == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT); | |
597 | z80_bus_cmd(Release); | |
598 | } | |
599 | return rc; | |
600 | } | |
601 | ||
602 | ||
603 | uint8_t z80_memfifo_getc_wait(const fifo_t f) | |
604 | { | |
605 | uint8_t rc, idx; | |
606 | ||
607 | while (z80_memfifo_is_empty(f)) | |
608 | ; | |
609 | ||
610 | z80_bus_cmd(Request); | |
611 | idx = fifo_dsc[f].idx_out; | |
612 | rc = z80_read(fifo_dsc[f].base+idx); | |
613 | fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; | |
614 | z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); | |
615 | z80_bus_cmd(Release); | |
616 | ||
617 | return rc; | |
618 | } | |
619 | ||
620 | int z80_memfifo_getc(const fifo_t f) | |
621 | { | |
622 | int rc = -1; | |
623 | ||
624 | if (fifo_dsc[f].base != 0) { | |
625 | uint8_t idx = fifo_dsc[f].idx_out; | |
626 | z80_bus_cmd(Request); | |
627 | if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) { | |
628 | rc = z80_read(fifo_dsc[f].base+idx); | |
629 | fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; | |
630 | z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); | |
631 | } | |
632 | z80_bus_cmd(Release); | |
633 | } | |
634 | ||
635 | return rc; | |
636 | } | |
637 | ||
638 | ||
639 | void z80_memfifo_putc(fifo_t f, uint8_t val) | |
640 | { | |
641 | int idx; | |
642 | ||
643 | while (z80_memfifo_is_full(f)) | |
644 | ; | |
645 | ||
646 | z80_bus_cmd(Request); | |
647 | idx = fifo_dsc[f].idx_in; | |
648 | z80_write(fifo_dsc[f].base+idx, val); | |
649 | fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask; | |
650 | z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in); | |
651 | z80_bus_cmd(Release); | |
652 | } |