]> cloudbase.mooo.com Git - z180-stamp.git/blame_incremental - avr/timer.c
Remove memory test and bank manager.
[z180-stamp.git] / avr / timer.c
... / ...
CommitLineData
1/*
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include "common.h"
8#include <avr/interrupt.h>
9#include <util/atomic.h>
10#include "time.h"
11#include "timer.h"
12
13/* timer interrupt/overflow counter */
14/* counts up every ms. */
15static volatile
16uint32_t timestamp;
17
18/*
19 * 1000Hz timer interrupt generated by OC3A
20 */
21ISR(TIMER3_COMPA_vect)
22{
23 static int_fast8_t tick_10ms;
24 static int_fast8_t tick_1s;
25 int_fast8_t i, j;
26
27 extern void disk_timerproc(void);
28
29 timestamp++;
30
31 i = tick_10ms + 1;
32 if (i == 10) {
33 Stat |= S_10MS_TO;
34
35 /* Drive timer procedure of low level disk I/O module */
36 disk_timerproc();
37
38 j = tick_1s - 1;
39 if (j == 0) {
40 system_tick();
41 j = 100;
42 }
43 tick_1s = j;
44 i = 0;
45 }
46 tick_10ms = i;
47}
48
49
50/*--------------------------------------------------------------------------*/
51
52#if 0
53void timer_setup(void)
54{
55
56 /* Clock */
57 CLKPR = _BV(CLKPCE);
58 CLKPR = 0;
59
60 /* Timer */
61
62 OCR1A = F_CPU / 1000 - 1; // Timer1: 1000Hz interval (OC1A)
63 TCCR1B = 0b00001001;
64 TIMSK1 = _BV(OCIE1A); // Enable TC1.oca interrupt
65}
66#endif
67
68/*--------------------------------------------------------------------------*/
69
70uint32_t get_timer(uint32_t base)
71{
72 uint32_t ret;
73 ATOMIC_BLOCK(ATOMIC_FORCEON)
74 {
75 ret = timestamp;
76 }
77 return ret - base;
78}