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[z180-stamp.git] / avr / z180-serv.c
1 /*
2 * (C) Copyright 2014-2016 Leo C. <erbl259-lmu@yahoo.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include "z180-serv.h"
8 #include "common.h"
9 #include <stdlib.h>
10 #include <string.h>
11 #include <stdbool.h>
12 #include <util/atomic.h>
13
14 #include "config.h"
15 #include "background.h"
16 #include "env.h"
17 #include "ff.h"
18 #include "serial.h"
19 #include "z80-if.h"
20 #include "debug.h"
21 #include "print-utils.h"
22 #include "timer.h"
23 #include "time.h"
24 #include "bcd.h"
25 #include "rtc.h"
26
27 #define DEBUG_CPM_SDIO 0 /* set to 1 to debug */
28
29 #define debug_cpmsd(fmt, args...) \
30 debug_cond(DEBUG_CPM_SDIO, fmt, ##args)
31
32
33 /*--------------------------------------------------------------------------*/
34
35 struct msg_item {
36 uint8_t fct;
37 uint8_t sub_min, sub_max;
38 void (*func)(uint8_t, int, uint8_t *);
39 };
40
41 uint32_t msg_to_addr(uint8_t *msg)
42 {
43 union {
44 uint32_t as32;
45 uint8_t as8[4];
46 } addr;
47
48 addr.as8[0] = msg[0];
49 addr.as8[1] = msg[1];
50 addr.as8[2] = msg[2];
51 addr.as8[3] = 0;
52
53 return addr.as32;
54 }
55
56
57 static int msg_xmit_header(uint8_t func, uint8_t subf, int len)
58 {
59 z80_memfifo_putc(fifo_msgout, 0xAE);
60 z80_memfifo_putc(fifo_msgout, len+2);
61 z80_memfifo_putc(fifo_msgout, func);
62 z80_memfifo_putc(fifo_msgout, subf);
63
64 return 0;
65 }
66
67 int msg_xmit(uint8_t func, uint8_t subf, int len, uint8_t *msg)
68 {
69 msg_xmit_header(func, subf, len);
70 while (len--)
71 z80_memfifo_putc(fifo_msgout, *msg++);
72
73 return 0;
74 }
75
76 void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
77 {
78 (void)len;
79
80 z80_memfifo_init(subf, msg_to_addr(msg));
81 }
82
83
84 void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
85 {
86 (void)subf;
87
88 while (len--)
89 putchar(*msg++);
90 }
91
92 /* echo message */
93 void do_msg_echo(uint8_t subf, int len, uint8_t * msg)
94 {
95 (void)subf;
96
97 /* send re-echo */
98 msg_xmit(1, 3, len, msg);
99 }
100
101 /* get timer */
102 void do_msg_get_timer(uint8_t subf, int len, uint8_t * msg)
103 {
104 uint32_t time_ms = (len >= 4) ? *(uint32_t *) msg : 0;
105
106 time_ms = get_timer(time_ms);
107 msg_xmit(3, subf, sizeof(time_ms), (uint8_t *) &time_ms);
108 }
109
110 /* ---------------------------------------------------------------------------*/
111
112 #define CPM_DAY_OFFSET ((1978-1900) * 365 + 19) /* 19 leap years */
113
114 /*
115 * Convert CP/M time stamp to a broken-down time structure
116 *
117 */
118 int mk_date_time (int len, uint8_t *msg, struct tm *tmp)
119 {
120 time_t stamp;
121
122 if (len != 5)
123 return -1;
124
125 /* days since 2000-01-01 */
126 long days = msg[3] + (msg[4] << 8) - 8036;
127
128 if (days < 0)
129 return -1;
130
131 stamp = days * ONE_DAY;
132 stamp += bcd2bin(msg[0]);
133 stamp += bcd2bin(msg[1]) * 60 ;
134 stamp += bcd2bin(msg[2]) * 3600L;
135 gmtime_r(&stamp, tmp);
136 return 0;
137 }
138
139 void mk_cpm_time(struct tm *tmp, uint8_t cpm_time[5])
140 {
141 uint16_t days = 1;
142 uint_fast8_t leap=2;
143
144 for (int year=78; year < tmp->tm_year; year++) {
145 days = days + 365 + (leap == 0);
146 leap = (leap+1)%4;
147 }
148 days += tmp->tm_yday;
149
150 cpm_time[0] = bin2bcd(tmp->tm_sec);
151 cpm_time[1] = bin2bcd(tmp->tm_min);
152 cpm_time[2] = bin2bcd(tmp->tm_hour);
153 cpm_time[3] = days;
154 cpm_time[4] = days >> 8;
155 }
156
157 /* get/set cp/m time */
158 void do_msg_get_set_time(uint8_t subf, int len, uint8_t * msg)
159 {
160 struct tm t;
161 uint8_t cpm_time[5];
162 int rc;
163
164 memset(cpm_time, 0, ARRAY_SIZE(cpm_time));
165
166 switch (subf) {
167 case 3: /* set date & time */
168 /* initialize t with current time */
169 rc = rtc_get (&t);
170
171 if (rc >= 0) {
172 /* insert new date & time */
173 if (mk_date_time (len, msg, &t) != 0) {
174 my_puts_P(PSTR("## set_time: Bad date format\n"));
175 break;
176 }
177
178 time_t time;
179 time = mk_gmtime(&t);
180 gmtime_r(&time, &t);
181
182 /* and write to RTC */
183 rc = rtc_set (&t);
184 if(rc)
185 my_puts_P(PSTR("## set_time: Set date failed\n"));
186 } else {
187 my_puts_P(PSTR("## set_time: Get date failed\n"));
188 }
189 /* FALL TROUGH */
190 case 2: /* get date & time */
191 rc = rtc_get (&t);
192 if (rc >= 0) {
193 time_t time;
194 time = mk_gmtime(&t);
195 //mktime(&t);
196 gmtime_r(&time, &t);
197
198 mk_cpm_time(&t, cpm_time);
199 } else {
200 my_puts_P(PSTR("## get_time: Get date failed\n"));
201 }
202 break;
203 }
204
205 msg_xmit(3, subf, sizeof(cpm_time), cpm_time);
206 }
207
208 /* ---------------------------------------------------------------------------*/
209
210 static uint8_t drv;
211 static uint8_t disk_buffer[CONFIG_CPM_BLOCK_SIZE];
212 static struct cpm_drive_s drv_table[CONFIG_CPM_MAX_DRIVE];
213 static int handle_cpm_drv_to;
214
215 typedef enum {SINGLE, START, MIDDLE, END} dbgmsg_t;
216
217 void drv_debug(dbgmsg_t phase, const FLASH char *const fmt, ...) \
218 {
219 struct cpm_drive_s *dp = &drv_table[drv];
220
221 if (dp->opt & DRV_OPT_DEBUG) {
222
223 va_list ap;
224 va_start (ap, fmt);
225
226 if (phase == SINGLE || phase == START)
227 printf_P(PSTR("# %7lu dsk%d: "), get_timer(0), drv);
228
229 vfprintf_P (stdout, fmt, ap);
230
231 if (phase == SINGLE || phase == END)
232 putc('\n', stdout);
233
234 va_end (ap);
235 }
236 }
237
238 int drv_list(void)
239 {
240 for (uint8_t i = 0; i < CONFIG_CPM_MAX_DRIVE; i++) {
241 struct cpm_drive_s * p = &drv_table[i];
242 if (p->img_name) {
243 printf_P(PSTR(" dsk%d: %2s %3s attached to %s\n"), i,
244 p->opt&DRV_OPT_RO ? "RO":"RW", p->opt&DRV_OPT_DEBUG ? "DBG":"",
245 p->img_name);
246 }
247 }
248 return 0;
249 }
250
251 int drv_detach(uint8_t unit)
252 {
253 drv = unit;
254 if (drv < CONFIG_CPM_MAX_DRIVE) {
255 struct cpm_drive_s *p = &drv_table[drv];
256
257 drv_debug(SINGLE, PSTR("detach from '%s'"), p->img_name ? p->img_name : "-");
258
259 if (p->img_name) {
260 f_close(&p->fd);
261 free(p->img_name);
262 p->opt = 0;
263 p->flags &= ~DRV_FLG_DIRTY;
264 p->img_name = NULL;
265
266 uint32_t scb = getenv_ulong(ENV_CPM3_SCB, 16, 0);
267 if (scb && (z80_bus_cmd(Request) & ZST_ACQUIRED)) {
268 z80_write(scb + 0xf0, 0xff);
269 z80_write(p->dph + 11, 0xff);
270 z80_bus_cmd(Release);
271 }
272 }
273 }
274 return 0;
275 }
276
277 static int drv_find_file_attached(const char *fn)
278 {
279 for (uint8_t i = 0; i < CONFIG_CPM_MAX_DRIVE; i++) {
280 struct cpm_drive_s *p = &drv_table[i];
281 if (p->img_name && !strcmp(fn, p->img_name)) {
282 return i;
283 }
284 }
285 return -1;
286 }
287
288 int drv_attach(uint8_t unit, const char *filename, drv_opt_t options)
289 {
290 int res;
291
292 drv = unit;
293 if (drv >= CONFIG_CPM_MAX_DRIVE)
294 return AT_RANGE;
295
296 struct cpm_drive_s *p = &drv_table[drv];
297
298 if (options & DRV_OPT_REATTATCH) {
299 if (filename) {
300 return AT_ERROR;
301 }
302
303 if (!p->img_name) {
304 return AT_NOT;
305 }
306
307 /* change options */
308 if ((p->opt ^ options) & DRV_OPT_RO) {
309 f_close(&p->fd);
310 res = f_open(&p->fd, p->img_name,
311 FA_READ | (options&DRV_OPT_RO ? 0 : FA_WRITE));
312 }
313
314 p->opt = options & ~DRV_OPT_REATTATCH;
315
316 } else {
317
318 if (p->img_name)
319 return AT_ALREADY;
320 if (drv_find_file_attached(filename) >= 0)
321 return AT_OTHER;
322
323 p->opt = options;
324
325 /* new attachment */
326
327 if ((p->img_name = strdup(filename)) == NULL)
328 return AT_NOMEM;
329
330 res = f_open(&p->fd, p->img_name,
331 FA_READ | (options&DRV_OPT_RO ? 0 : FA_WRITE));
332
333 if (!res && f_size(&p->fd) < CONFIG_CPM_DISKSIZE) {
334 #if 0
335 unsigned int bw;
336 debug_cpmsd(" expanding image file from %ld to %ld\n",
337 f_size(&p->fd), CONFIG_CPM_DISKSIZE);
338
339 res = f_lseek(&p->fd, CONFIG_CPM_DISKSIZE-CONFIG_CPM_BLOCK_SIZE);
340 if (!res) {
341 memset(disk_buffer, 0xe5, CONFIG_CPM_BLOCK_SIZE);
342 res = f_write(&p->fd, disk_buffer, CONFIG_CPM_BLOCK_SIZE, &bw);
343 if (res || bw < CONFIG_CPM_BLOCK_SIZE) {
344 debug_cpmsd(" failed! res: %d, bytes written: %u\n", res, bw);
345 }
346 p->flags |= DRV_FLG_DIRTY;
347 bg_setstat(handle_cpm_drv_to, 1);
348 }
349 #else
350 drv_debug(SINGLE, PSTR("wrong image file size: %ld, should be %ld"),
351 f_size(&p->fd), CONFIG_CPM_DISKSIZE);
352 res = 64;
353 #endif
354 }
355 if (res) {
356 drv_detach(drv);
357 return AT_OPEN;
358 }
359 }
360
361 return AT_OK;
362 }
363
364
365 int cpm_drv_to(int state)
366 {
367 static uint32_t ts;
368
369 switch(state) {
370 case 0:
371 break;
372
373 case 1:
374 ts = get_timer(0);
375 state = 2;
376 break;
377
378 case 2:
379 if (get_timer(ts) > 1000) {
380 for (uint_fast8_t i=0; i < CONFIG_CPM_MAX_DRIVE; i++) {
381 if (drv_table[i].flags & DRV_FLG_DIRTY) {
382 drv_table[i].flags &= ~DRV_FLG_DIRTY;
383 f_sync(&drv_table[i].fd);
384 drv = i;
385 drv_debug(SINGLE, PSTR("f_sync"));
386 }
387 }
388 state = 0;
389 }
390 }
391 return state;
392 }
393
394 static const FLASH char * const FLASH rc_messages[] = {
395 FSTR("OK"),
396 FSTR("Internal error: wrong message len"), /* 01 */
397 FSTR("Invalid relative drive #"), /* 02 */
398 FSTR("Bus timeout"), /* 03 */
399 FSTR("Access byond disk size"), /* 04 */
400 FSTR("Write protect"), /* 05 */
401 FSTR("No media"), /* 06 */
402 FSTR("R/W address == 0 !!!!"), /* 07 */
403 };
404
405 void msg_cpm_result(uint8_t subf, uint8_t rc, int res)
406 {
407 uint8_t result_msg[3];
408
409 if (res)
410 rc |= 0x80;
411
412 result_msg[0] = rc;
413 result_msg[1] = res;
414 result_msg[2] = res >> 8;
415
416 msg_xmit(2, subf, sizeof(result_msg), result_msg);
417
418 if (rc)
419 drv_debug(END, PSTR(" rc: %.02x/%d, '%S'"),
420 rc, res, rc_messages[rc & 0x7f]);
421 else
422 drv_debug(END, PSTR(""));
423
424 }
425
426 /*
427 db 2 ; disk command
428 ds 1 ; subcommand (login/read/write)
429 ds 1 ; @adrv (8 bits) +0
430 ds 1 ; @rdrv (8 bits) +1
431 ds 3 ; @xdph (24 bits) +2
432 */
433
434 void do_msg_cpm_login(uint8_t subf, int len, uint8_t * msg)
435 {
436 struct cpm_drive_s *dp;
437 FRESULT res = 0;
438
439 (void)subf;
440
441 /* Get relative drive number */
442 drv = msg[1];
443 drv_debug(START, PSTR("login"));
444
445 if (len != 5) {
446 return msg_cpm_result(subf, 0x01, res);
447 }
448
449 if ( drv >= CONFIG_CPM_MAX_DRIVE) {
450 /* invalid relative drive number */
451 return msg_cpm_result(subf, 0x02, res);
452 }
453
454 dp = &drv_table[drv];
455 dp->flags &= ~DRV_FLG_OPEN;
456 dp->dph = ((uint32_t)msg[4] << 16) + ((uint16_t)msg[3] << 8) + msg[2];
457
458 if (dp->img_name == NULL) {
459 /* no file attached */
460 return msg_cpm_result(subf, 0x06, res);
461 }
462
463 f_close(&dp->fd);
464 res = f_open(&dp->fd, dp->img_name,
465 FA_READ | (dp->opt&DRV_OPT_RO ? 0 : FA_WRITE));
466
467 dp->flags |= DRV_FLG_OPEN;
468
469 /* send result*/
470 msg_cpm_result(subf, 0x00, res);
471 }
472
473
474 /*
475 db 2 ; disk command
476 ds 1 ; subcommand (login/read/write)
477 ds 1 ; @adrv (8 bits) +0
478 ds 1 ; @rdrv (8 bits) +1
479 ds 2 ; @trk (16 bits) +2
480 ds 2 ; @sect(16 bits) +4
481 ds 1 ; @cnt (8 bits) +6
482 ds 3 ; phys. transfer addr +7
483 */
484
485 #define ADRV 0
486 #define RDRV 1
487 #define TRK 2
488 #define SEC 4
489 #define CNT 6
490 #define ADDR 7
491
492 void do_msg_cpm_rw(uint8_t subf, int len, uint8_t * msg)
493 {
494 struct cpm_drive_s *dp;
495 uint32_t addr;
496 uint32_t pos;
497 uint16_t track;
498 uint16_t sec;
499 uint8_t secs;
500 bool dowrite;
501 FRESULT res = 0;
502 uint8_t rc = 0;
503 bool buserr = 0;
504
505 drv = msg[RDRV];
506 dowrite = (subf == 2);
507
508 drv_debug(START, PSTR("%2S"), dowrite ? PSTR("W ") : PSTR(" R"));
509
510 if (len != 10) {
511 return msg_cpm_result(subf, 0x01, res);
512 }
513 if ( drv>= CONFIG_CPM_MAX_DRIVE) {
514 return msg_cpm_result(subf, 0x02, res);
515 }
516
517 dp = &drv_table[drv];
518 track = (uint16_t)(msg[TRK+1] << 8) + msg[TRK];
519 sec = (uint16_t)(msg[SEC+1] << 8) + msg[SEC];
520 secs = msg[CNT];
521 addr = ((uint32_t)msg[ADDR+2] << 16) + ((uint16_t)msg[ADDR+1] << 8) + msg[ADDR];
522
523 if (dp->img_name == NULL) {
524 /* no media */
525 return msg_cpm_result(subf, 0x06, res);
526 }
527
528 /* TODO: tracks per sector from dpb */
529 pos = (track * 8UL + sec) * CONFIG_CPM_BLOCK_SIZE;
530
531 drv_debug(MIDDLE, PSTR(" T:%4d, S:%2d, cnt:%2d, lba: %.8lx, addr: %.5lx"),
532 track, sec, secs, pos, addr);
533
534 if (addr == 0) {
535 return msg_cpm_result(subf, 0x07, res);
536 }
537
538 if (dowrite && dp->opt & DRV_OPT_RO) {
539 return msg_cpm_result(subf, 0x05, res);
540 }
541
542
543 if (pos + secs * CONFIG_CPM_BLOCK_SIZE > CONFIG_CPM_DISKSIZE) {
544 drv_debug(MIDDLE, PSTR(" access > DISKSIZE:%.8lx!"),
545 CONFIG_CPM_DISKSIZE);
546 return msg_cpm_result(subf, 0x04, res);
547 }
548
549 res = f_lseek(&dp->fd, pos);
550
551 while (!res && secs--) {
552 unsigned int brw;
553 if (dowrite) {
554 if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
555 buserr = 1;
556 break;
557 } else {
558 z80_read_block(disk_buffer, addr, CONFIG_CPM_BLOCK_SIZE);
559 z80_bus_cmd(Release);
560 }
561 res = f_write(&dp->fd, disk_buffer, CONFIG_CPM_BLOCK_SIZE, &brw);
562 } else {
563 res = f_read(&dp->fd, disk_buffer, CONFIG_CPM_BLOCK_SIZE, &brw);
564 if (res == FR_OK) {
565 if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
566 buserr = 1;
567 break;
568 } else {
569 z80_write_block(disk_buffer, addr, CONFIG_CPM_BLOCK_SIZE);
570 z80_bus_cmd(Release);
571 }
572 }
573 }
574 if (brw != CONFIG_CPM_BLOCK_SIZE) {
575 drv_debug(MIDDLE, PSTR(" short rd/wr: res: %d, brw: %u"),
576 res, brw);
577 res = 64;
578 }
579 addr += CONFIG_CPM_BLOCK_SIZE;
580 }
581
582 if (dowrite && !res) {
583 dp->flags |= DRV_FLG_DIRTY;
584 bg_setstat(handle_cpm_drv_to, 1);
585 }
586
587 if (buserr) {
588 /* Bus timeout. how can this happen? */
589 rc = 0x03;
590 }
591
592 /* send result*/
593 msg_cpm_result(subf, rc, res);
594 }
595
596
597 const FLASH struct msg_item z80_messages[] =
598 {
599 { 0, /* fct nr. */
600 1, 3, /* sub fct nr. from, to */
601 do_msg_ini_memfifo},
602 { 1,
603 1, 1,
604 do_msg_char_out},
605 { 1,
606 2, 2,
607 do_msg_echo},
608 { 2,
609 0, 0,
610 do_msg_cpm_login},
611 { 2,
612 1, 2,
613 do_msg_cpm_rw},
614 { 3,
615 1, 1,
616 do_msg_get_timer},
617 { 3,
618 2, 3, /* 2: get, 3: set time and date */
619 do_msg_get_set_time},
620 { 0xff, /* end mark */
621 0, 0,
622 0},
623
624 };
625
626
627
628
629 void do_message(int len, uint8_t *msg)
630 {
631 uint8_t fct, sub_fct;
632 int_fast8_t i = 0;
633
634 if (len >= 2) {
635 fct = *msg++;
636 sub_fct = *msg++;
637 len -= 2;
638
639 while (fct != z80_messages[i].fct) {
640 if (z80_messages[i].fct == 0xff) {
641 DBG_P(1, "do_message: Unknown function: %i, %i\n",
642 fct, sub_fct);
643 return; /* TODO: unknown message # */
644 }
645
646 ++i;
647 }
648
649 while (fct == z80_messages[i].fct) {
650 if (sub_fct >= z80_messages[i].sub_min &&
651 sub_fct <= z80_messages[i].sub_max )
652 break;
653 ++i;
654 }
655
656 if (z80_messages[i].fct != fct) {
657 DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
658 fct, sub_fct);
659 return; /* TODO: unknown message sub# */
660 }
661
662 (z80_messages[i].func)(sub_fct, len, msg);
663
664
665 } else {
666 /* TODO: error */
667 DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
668 }
669 }
670
671
672
673 #define CTRBUF_LEN 256
674
675 void check_msg_fifo(void)
676 {
677 int ch;
678 static int_fast8_t state;
679 static int msglen,idx;
680 static uint8_t buffer[CTRBUF_LEN];
681
682 while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
683 switch (state) {
684 case 0: /* wait for start of message */
685 if (ch == 0xAE) { /* TODO: magic number */
686 msglen = 0;
687 idx = 0;
688 state = 1;
689 }
690 break;
691 case 1: /* get msg len */
692 if (ch > 0 && ch <= CTRBUF_LEN) {
693 msglen = ch;
694 state = 2;
695 } else
696 state = 0;
697 break;
698 case 2: /* get message */
699 buffer[idx++] = ch;
700 if (idx == msglen) {
701 do_message(msglen, buffer);
702 state = 0;
703 }
704 break;
705 }
706 }
707 }
708
709
710 int msg_handling(int state)
711 {
712 bool pending;
713
714 ATOMIC_BLOCK(ATOMIC_FORCEON) {
715 pending = (Stat & S_MSG_PENDING) != 0;
716 Stat &= ~S_MSG_PENDING;
717 }
718
719 if (pending) {
720 uint8_t init_request;
721 z80_bus_cmd(Request);
722 init_request = z80_read(0x43);
723 z80_bus_cmd(Release);
724 if ( init_request != 0) {
725 /* Get address of fifo 0 */
726 z80_bus_cmd(Request);
727 uint32_t fifo_addr = z80_read(0x40) +
728 ((uint16_t) z80_read(0x40+1) << 8) +
729 ((uint32_t) z80_read(0x40+2) << 16);
730 z80_write(0x43, 0);
731 z80_bus_cmd(Release);
732
733 if (fifo_addr != 0) {
734 z80_memfifo_init(fifo_msgin, fifo_addr);
735 state = 1;
736 } else
737 state = 0;
738
739 } else {
740 check_msg_fifo();
741 }
742 }
743
744 return state;
745 }
746
747
748 static int handle_msg_handling;
749
750 void setup_z180_serv(void)
751 {
752
753 handle_msg_handling = bg_register(msg_handling, 0);
754 handle_cpm_drv_to = bg_register(cpm_drv_to, 0);
755 }
756
757 void restart_z180_serv(void)
758 {
759 z80_bus_cmd(Request);
760 z80_memset(0x40, 0, 4);
761 z80_bus_cmd(Release);
762
763 for (int i = 0; i < NUM_FIFOS; i++)
764 z80_memfifo_init(i, 0);
765 bg_setstat(handle_msg_handling, 0);
766
767 }
768
769 #if 0
770 /*--------------------------------------------------------------------------*/
771
772 const FLASH uint8_t iniprog[] = {
773 0xAF, // xor a
774 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
775 0x3E, 0x30, // ld a,030h
776 0xED, 0x39, 0x32 //out0 (dcntl),a ;0 mem, max i/0 wait states
777 };
778
779 const FLASH uint8_t sertest[] = {
780 0xAF, // xor a
781 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
782 0x3E, 0x30, // ld a,030h
783 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
784 0x3E, 0x80, // ld a,M_MPBT ;no MP, PS=10, DR=16, SS=0
785 0xED, 0x39, 0x03, // out0 (cntlb1),a
786 0x3E, 0x64, // ld a,M_RE + M_TE + M_MOD2 ;
787 0xED, 0x39, 0x01, // out0 (cntla1),a
788 0x3E, 0x00, // ld a,0
789 0xED, 0x39, 0x05, // out0 (stat1),a ;Enable rx interrupts
790 0xED, 0x38, 0x05, //l0:in0 a,(stat1)
791 0xE6, 0x80, // and 80h
792 0x28, 0xF9, // jr z,l0
793 0xED, 0x00, 0x09, // in0 b,(rdr1)
794 0xED, 0x38, 0x05, //l1:in0 a,(stat1)
795 0xE6, 0x02, // and 02h
796 0x28, 0xF9, // jr z,l1
797 0xED, 0x01, 0x07, // out0 (tdr1),b
798 0x18, 0xEA, // jr l0
799 };
800
801 const FLASH uint8_t test1[] = {
802 0xAF, // xor a
803 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
804 0x3E, 0x30, // ld a,030h
805 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
806 0x21, 0x1E, 0x00, // ld hl,dmclrt ;load DMA registers
807 0x06, 0x08, // ld b,dmct_e-dmclrt
808 0x0E, 0x20, // ld c,sar0l
809 0xED, 0x93, // otimr
810 0x3E, 0xC3, // ld a,0c3h ;dst +1, src +1, burst
811 0xED, 0x39, 0x31, // out0 (dmode),a ;
812 0x3E, 0x62, // ld a,062h ;enable dma0,
813 0xED, 0x39, 0x30, //cl_1: out0 (dstat),a ;copy 64k
814 0x18, 0xFB, // jr cl_1 ;
815 0x00, 0x00, //dmclrt: dw 0 ;src (inc)
816 0x00, // db 0 ;src
817 0x00, 0x00, // dw 0 ;dst (inc),
818 0x00, // db 0 ;dst
819 0x00, 0x00, // dw 0 ;count (64k)
820 };
821 #endif
Z180 Stamp Monitor