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1 page 200
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3
4 extrn buf.init
5 extrn isv_sw
6
7
8 global ser.init
9 global ser.ist,ser.in
10 global ser.ost,ser.out
11
12 ;TODO: define a trampoline area somewhere in top ram.
13 rtxisvjmp equ 0FF60h ;momentan frei...
14
15 include config.inc
16 include z180reg.inc
17
18
19 ;-----------------------------------------------------
20
21 dseg
22
23 buf_start:
24 mkbuf ser1.inbuf,s1.rx_len
25 mkbuf ser1.outbuf,s1.tx_len
26 buf_end:
27
28
29
30 ;-----------------------------------------------------
31
32 cseg
33 ;
34 ; Init Serial I/O for console input and output (ASCI1)
35 ;
36
37
38 ser.init:
39 ; ld a,i
40 ; push af ;save IFF
41 ; di
42
43 xor a ;
44 out0 (stat1),a ;Disable rx/tx interrupts
45
46 ld hl,rxtx_src ;move rx and tx isv to common ram
47 ld de,rxtx_dst ;
48 ld bc,rxtx_src_e-rxtx_src ;
49 ldir ;
50
51 ld hl,rtxisvjmp ;rx/tx int vector
52 ld (ivtab + IV$ASCI1),hl;
53 ld a,0cdh ;
54 ld (rtxisvjmp),a ;
55 ld hl,isv_sw ;
56 ld (rtxisvjmp + 1),hl ;
57 ld hl,rxtxisv ;
58 ld (rtxisvjmp + 3),hl ;
59
60 ; ASCI1: 8N1, highest baudrate (56700), CTS disabled
61
62 ld a,M_MPBT
63 out0 (cntlb1),a
64 ld a,M_RE + M_TE + M_MOD2
65 out0 (cntla1),a
66 ld a,M_RIE
67 out0 (stat1),a ;Enable rx interrupts
68
69 ld ix,ser1.inbuf
70 ld a,ser1.inbuf.mask
71 call buf.init
72 ld ix,ser1.outbuf
73 ld a,ser1.outbuf.mask
74 call buf.init
75
76 ; pop af
77 ; ret po
78 ; ei
79 ret ;
80
81 ser.ist:
82 push ix
83 ld ix,ser1.inbuf ;
84
85 buf.empty:
86 ld a,(ix+o.in_idx) ;
87 sub (ix+o.out_idx) ;
88 pop ix
89 ret z
90 or 0ffh
91 ret
92
93 ser.in:
94 push hl ;11
95 push de ;11
96 ld hl,ser1.inbuf-1 ; 9 hl = &rx.out_idx
97 ld a,(hl) ; 6 a = rx.out_idx
98 dec hl ; 4 hl = &rx.in_idx
99 jr bg.w1
100 bg.wait:
101 halt
102 bg.w1:
103 cp (hl) ; 6 while (out_idx==in_idx)
104 jr z,bg.wait ; 6 (/8) ;
105
106 ld e,a ; 4
107 ld d,0 ; 6
108 inc de
109 inc de
110
111 ex de,hl ; 3
112 add hl,de ;10
113 ld l,(hl) ; 6
114 ex de,hl ; 3
115
116 inc a ; 4
117 dec hl ; 4
118 and (hl) ; 6
119 inc hl ; 4
120 inc hl ; 4
121 ld (hl),a ; 7
122
123 ld a,e ; 4
124 pop de ; 9
125 pop hl ; 9
126 ret ; 9
127 ; 153
128
129 ser.ost:
130 push ix
131 ld ix,ser1.outbuf ;
132 buf.full:
133 ld a,(ix+o.in_idx) ;
134 inc a
135 and (ix+o.mask)
136 sub (ix+o.out_idx) ;
137 pop ix
138 ret z
139 or 0ffh
140 ret
141
142
143 ser.out:
144 push ix
145 ld ix,ser1.outbuf ;
146 buf.put:
147 push hl ;
148 push bc
149 push ix
150 pop hl
151 ld a,c
152 ld c,(ix+o.in_idx) ;
153 ld b,0
154 add hl,bc
155 ld (hl),a
156
157 ld a,c ;
158 inc a
159 and (ix+o.mask)
160 bp.wait:
161 cp (ix+o.out_idx) ;
162 jr z,bp.wait
163 ld (ix+o.in_idx),a
164
165 di ;036f
166 in0 a,(stat1) ;0374
167 set TIE,a ;0377
168 out0 (stat1),a ;0379
169 ei ;037c
170
171 ld a,b
172 pop bc
173 pop hl
174 pop ix
175 ret
176
177
178 ;------------------------------------------
179 ; ASCI 1 Transmit/Receive interupt routines
180 ; moved to common ram
181
182 rxtx_src:
183 dseg
184 rxtx_dst: ; (0c097h) old
185
186 rxtxisv:
187 inidat
188 in0 a,(stat1) ;receive flag set?
189 jp p,txisv ;
190
191 in0 d,(rdr1) ;todo: break detection
192 bit FE,a ;framing error?
193 jr nz,??ri_1
194
195 push ix
196 ld ix,ser1.inbuf ;
197 ld hl,ser1.inbuf ;
198 ld c,(ix+o.in_idx) ;
199 ld b,0
200 add hl,bc
201
202 ld a,c ;
203 inc a
204 and (ix+o.mask)
205 cp (ix+o.out_idx) ;
206 jr z,??ri_0
207 ld (hl),d
208 ld (ix+o.in_idx),a
209 ??ri_0:
210 pop ix
211 ??ri_1:
212 in0 a,(cntla1) ;0705 c0c0
213 res EFR,a ;0708
214 out0 (cntla1),a ;070a
215 ret
216
217 inidate
218
219 txisv:
220 inidat
221 push ix
222 ld ix,ser1.outbuf ;
223
224 ld a,(ix+o.out_idx) ;
225 cp (ix+o.in_idx) ;
226 jr z,??ti_2
227
228 ld hl,ser1.outbuf ;
229 add a,l
230 ld l,a
231 jr nc,??ti_1
232 inc h
233 ??ti_1:
234 ld l,(hl)
235 out0 (tdr1),l ;071b
236
237 ld a,(ix+o.out_idx) ;
238 inc a
239 and (ix+o.mask)
240 ld (ix+o.out_idx),a
241 jr ??ti_3
242 ??ti_2:
243 in0 a,(stat1) ;0730 disable tx-int
244 res TIE,a ;0733
245 out0 (stat1),a ;0735
246 ??ti_3:
247 pop ix
248 ret
249
250 inidate
251
252 cseg
253 rxtx_src_e:
254
255
256 end
257
258