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1 /*
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include "common.h"
8 #include <stdlib.h>
9 #include <string.h>
10 #include <stdbool.h>
11 #include <util/atomic.h>
12
13 #include "background.h"
14 #include "env.h"
15 #include "ff.h"
16 #include "serial.h"
17 #include "z80-if.h"
18 #include "debug.h"
19 #include "print-utils.h"
20 #include "z180-serv.h"
21 #include "timer.h"
22
23
24 #define DEBUG_CPM_SDIO 0 /* set to 1 to debug */
25
26 #define debug_cpmsd(fmt, args...) \
27 debug_cond(DEBUG_CPM_SDIO, fmt, ##args)
28
29
30
31 /*--------------------------------------------------------------------------*/
32
33
34 uint8_t z80_get_byte(uint32_t adr)
35 {
36 uint8_t data;
37
38 z80_bus_cmd(Request);
39 data = z80_read(adr);
40 z80_bus_cmd(Release);
41
42 return data;
43 }
44
45
46 /*--------------------------------------------------------------------------*/
47
48 struct msg_item {
49 uint8_t fct;
50 uint8_t sub_min, sub_max;
51 void (*func)(uint8_t, int, uint8_t *);
52 };
53
54 uint32_t msg_to_addr(uint8_t *msg)
55 {
56 union {
57 uint32_t as32;
58 uint8_t as8[4];
59 } addr;
60
61 addr.as8[0] = msg[0];
62 addr.as8[1] = msg[1];
63 addr.as8[2] = msg[2];
64 addr.as8[3] = 0;
65
66 return addr.as32;
67 }
68
69
70 static int msg_xmit_header(uint8_t func, uint8_t subf, int len)
71 {
72 z80_memfifo_putc(fifo_msgout, 0xAE);
73 z80_memfifo_putc(fifo_msgout, len+2);
74 z80_memfifo_putc(fifo_msgout, func);
75 z80_memfifo_putc(fifo_msgout, subf);
76
77 return 0;
78 }
79
80 int msg_xmit(uint8_t func, uint8_t subf, int len, uint8_t *msg)
81 {
82 msg_xmit_header(func, subf, len);
83 while (len--)
84 z80_memfifo_putc(fifo_msgout, *msg++);
85
86 return 0;
87 }
88
89 void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
90 {
91 (void)len;
92
93 z80_memfifo_init(subf, msg_to_addr(msg));
94 }
95
96
97 void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
98 {
99 (void)subf;
100
101 while (len--)
102 putchar(*msg++);
103 }
104
105 /* echo message */
106 void do_msg_echo(uint8_t subf, int len, uint8_t * msg)
107 {
108 (void)subf;
109
110 /* send re-echo */
111 msg_xmit(1, 3, len, msg);
112 }
113
114 /* ---------------------------------------------------------------------------*/
115
116 #define MAX_DRIVE 4
117 #define BLOCK_SIZE 512
118 #define TPA_BASE 0x10000
119 #define COMMON_BASE 0xC000
120
121 struct cpm_drive_s {
122 uint8_t drv;
123 uint8_t device;
124 char *img_name;
125 FIL fd;
126 };
127
128 static uint8_t disk_buffer[BLOCK_SIZE];
129 static struct cpm_drive_s drv_table[MAX_DRIVE];
130
131 /*
132 db 2 ; disk command
133 ds 1 ; subcommand (login/read/write)
134 ds 1 ; @adrv (8 bits) +0
135 ds 1 ; @rdrv (8 bits) +1
136 ds 3 ; @xdph (24 bits) +2
137 */
138
139 void do_msg_cpm_login(uint8_t subf, int len, uint8_t * msg)
140 {
141
142 FRESULT res = 0;
143 uint8_t rc = 0;
144 uint8_t drv;
145 char *np;
146 uint8_t result_msg[3];
147
148 (void)subf;
149
150 if (len != 5) { /* TODO: check adrv, rdrv */
151 rc = 0x01;
152 goto out;
153 }
154
155 debug_cpmsd("\n## %7lu login: %c:\n", get_timer(0), msg[0]+'A');
156
157
158 drv = msg[0];
159 if ( drv>= MAX_DRIVE) {
160 rc = 0x02;
161 goto out;
162 }
163
164 /*
165 uint32_t dph = ((uint32_t)msg[4] << 16) + ((uint16_t)msg[3] << 8) + msg[2];
166 */
167
168 if (drv_table[drv].img_name != NULL) {
169 debug_cpmsd("## %7lu close: '%s'\n", get_timer(0), drv_table[drv].img_name);
170 f_close(&drv_table[drv].fd);
171 free(drv_table[drv].img_name);
172 drv_table[drv].img_name = NULL;
173 }
174
175 strcpy_P((char *)disk_buffer, PSTR("dsk0"));
176 disk_buffer[3] = msg[0] + '0';
177 if (((np = getenv((char*)disk_buffer)) == NULL) ||
178 ((drv_table[drv].img_name = strdup(np)) == NULL)) {
179 rc = 0x03;
180 goto out;
181 }
182
183
184 res = f_open(&drv_table[drv].fd, drv_table[drv].img_name,
185 FA_WRITE | FA_READ);
186
187 debug_cpmsd("## %7lu open: '%s', (env: '%s'), res: %d\n", get_timer(0),
188 drv_table[drv].img_name, disk_buffer, res);
189
190 out:
191
192 if (res)
193 rc |= 0x80;
194
195 result_msg[0] = rc;
196 result_msg[1] = res;
197 result_msg[2] = res >> 8;
198
199 if (rc) {
200 debug_cpmsd("## %7lu error rc: %.02x, res: %d\n", get_timer(0), rc, res);
201 };
202
203 /* send result*/
204 msg_xmit(2, subf, sizeof(result_msg), result_msg);
205 }
206
207
208 /*
209 db 2 ; disk command
210 ds 1 ; subcommand (login/read/write)
211 ds 1 ; @adrv (8 bits) +0
212 ds 1 ; @rdrv (8 bits) +1
213 ds 2 ; @trk (16 bits) +2
214 ds 2 ; @sect(16 bits) +4
215 ds 1 ; @cnt (8 bits) +6
216 ds 3 ; phys. transfer addr +7
217 */
218
219 #define ADRV 0
220 #define RDRV 1
221 #define TRK 2
222 #define SEC 4
223 #define CNT 6
224 #define ADDR 7
225
226 void do_msg_cpm_rw(uint8_t subf, int len, uint8_t * msg)
227 {
228 uint8_t drv;
229 uint32_t addr;
230 uint32_t pos;
231 uint8_t secs;
232 bool dowrite = (subf == 2);
233 FRESULT res = 0;
234 uint8_t rc = 0;
235 bool buserr = 0;
236 uint8_t result_msg[3];
237
238 if (len != 10) { /* TODO: check adrv, rdrv */
239 rc = 0x01;
240 goto out;
241 }
242
243 drv = msg[ADRV];
244 if ( drv>= MAX_DRIVE) {
245 rc = 0x02;
246 goto out;
247 }
248
249 secs = msg[CNT];
250 addr = ((uint32_t)msg[ADDR+2] << 16) + ((uint16_t)msg[ADDR+1] << 8) + msg[ADDR];
251
252
253 /* TODO: tracks per sector from dpb */
254 pos = (((uint16_t)(msg[TRK+1] << 8) + msg[TRK]) * 8
255 + ((uint32_t)(msg[SEC+1] << 8) + msg[SEC])) * BLOCK_SIZE;
256
257 debug_cpmsd("## %7lu cpm_rw: %s %c: trk:%4d, sec: %d, pos: %.8lx, secs: %2d, "
258 "addr: %.5lx\n", get_timer(0), dowrite ? "write" : " read",
259 msg[ADRV]+'A', ((uint16_t)(msg[TRK+1] << 8) + msg[TRK]), msg[SEC],
260 pos, msg[CNT], addr);
261
262 res = f_lseek(&drv_table[drv].fd, pos);
263 while (!res && secs--) {
264 unsigned int cnt, br;
265
266 /* check bank boundary crossing */
267 cnt = 0;
268 if (addr < (TPA_BASE + COMMON_BASE) &&
269 (addr + BLOCK_SIZE) > (TPA_BASE + COMMON_BASE)) {
270 cnt = (TPA_BASE + COMMON_BASE) - addr;
271 }
272
273 if (cnt) {
274 debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr, cnt);
275 debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr+cnt-TPA_BASE, BLOCK_SIZE-cnt);
276 }
277
278 if (dowrite) {
279 if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
280 buserr = 1;
281 break;
282 } else {
283 if (cnt) {
284 z80_read_block(disk_buffer, addr, cnt);
285 addr = addr + cnt - TPA_BASE;
286 }
287 z80_read_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
288 z80_bus_cmd(Release);
289 }
290 res = f_write(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
291 } else {
292 res = f_read(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
293 if (res == FR_OK && br == BLOCK_SIZE) {
294 if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
295 buserr = 1;
296 break;
297 } else {
298 if (cnt) {
299 z80_write_block(disk_buffer, addr, cnt);
300 addr = addr + cnt - TPA_BASE;
301 }
302 z80_write_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
303 z80_bus_cmd(Release);
304 }
305 }
306 }
307
308 if (br != BLOCK_SIZE) {
309 debug_cpmsd("## %7lu f_read res: %d, bytes rd/wr: %u\n", get_timer(0), res, br);
310 dump_ram(disk_buffer, 0, 64, "Read Data");
311 res = -1;
312 }
313
314 addr += BLOCK_SIZE;
315 }
316
317 if (dowrite && !res)
318 res = f_sync(&drv_table[drv].fd);
319
320 out:
321 if (buserr) {
322 debug_cpmsd("Bus timeout\n");
323 rc = 0x03;
324 }
325 if (res)
326 rc |= 0x80;
327
328 result_msg[0] = rc;
329 result_msg[1] = res;
330 result_msg[2] = res >> 8;
331
332 if (rc) {
333 debug_cpmsd("###%7lu error rc: %.02x, res: %d\n", get_timer(0), rc, res);
334 }
335
336 /* send result*/
337 msg_xmit(2, subf, sizeof(result_msg), result_msg);
338 }
339
340
341 const FLASH struct msg_item z80_messages[] =
342 {
343 { 0, /* fct nr. */
344 1, 3, /* sub fct nr. from, to */
345 do_msg_ini_memfifo},
346 { 1,
347 1, 1,
348 do_msg_char_out},
349 { 1,
350 2, 2,
351 do_msg_echo},
352 { 2,
353 0, 0,
354 do_msg_cpm_login},
355 { 2,
356 1, 2,
357 do_msg_cpm_rw},
358 { 0xff, /* end mark */
359 0, 0,
360 0},
361
362 };
363
364
365
366
367 void do_message(int len, uint8_t *msg)
368 {
369 uint8_t fct, sub_fct;
370 int_fast8_t i = 0;
371
372 if (len >= 2) {
373 fct = *msg++;
374 sub_fct = *msg++;
375 len -= 2;
376
377 while (fct != z80_messages[i].fct) {
378 if (z80_messages[i].fct == 0xff) {
379 DBG_P(1, "do_message: Unknown function: %i, %i\n",
380 fct, sub_fct);
381 return; /* TODO: unknown message # */
382 }
383
384 ++i;
385 }
386
387 while (fct == z80_messages[i].fct) {
388 if (sub_fct >= z80_messages[i].sub_min &&
389 sub_fct <= z80_messages[i].sub_max )
390 break;
391 ++i;
392 }
393
394 if (z80_messages[i].fct != fct) {
395 DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
396 fct, sub_fct);
397 return; /* TODO: unknown message sub# */
398 }
399
400 (z80_messages[i].func)(sub_fct, len, msg);
401
402
403 } else {
404 /* TODO: error */
405 DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
406 }
407 }
408
409
410
411 #define CTRBUF_LEN 256
412
413 void check_msg_fifo(void)
414 {
415 int ch;
416 static int_fast8_t state;
417 static int msglen,idx;
418 static uint8_t buffer[CTRBUF_LEN];
419
420 while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
421 switch (state) {
422 case 0: /* wait for start of message */
423 if (ch == 0xAE) { /* TODO: magic number */
424 msglen = 0;
425 idx = 0;
426 state = 1;
427 }
428 break;
429 case 1: /* get msg len */
430 if (ch > 0 && ch <= CTRBUF_LEN) {
431 msglen = ch;
432 state = 2;
433 } else
434 state = 0;
435 break;
436 case 2: /* get message */
437 buffer[idx++] = ch;
438 if (idx == msglen) {
439 do_message(msglen, buffer);
440 state = 0;
441 }
442 break;
443 }
444 }
445 }
446
447
448 int msg_handling(int state)
449 {
450 uint8_t pending;
451
452 ATOMIC_BLOCK(ATOMIC_FORCEON) {
453 pending = (Stat & S_MSG_PENDING) != 0;
454 Stat &= ~S_MSG_PENDING;
455 }
456
457 if (pending) {
458 switch (state) {
459 case 0: /* need init */
460 /* Get address of fifo_list */
461 z80_bus_cmd(Request);
462 uint32_t fifo_list = z80_read(0x40) +
463 ((uint16_t) z80_read(0x41) << 8) +
464 ((uint32_t) z80_read(0x42) << 16);
465 z80_bus_cmd(Release);
466 if (fifo_list != 0) {
467 /* Get address of fifo 0 */
468 z80_bus_cmd(Request);
469 uint32_t fifo_addr = z80_read(fifo_list) +
470 ((uint16_t) z80_read(fifo_list+1) << 8) +
471 ((uint32_t) z80_read(fifo_list+2) << 16);
472 z80_bus_cmd(Release);
473 if (fifo_addr != 0) {
474 z80_memfifo_init(fifo_msgin, fifo_addr);
475 state = 1;
476 }
477 }
478 break;
479 case 1: /* awaiting messages */
480 check_msg_fifo();
481 break;
482 }
483 }
484
485 return state;
486 }
487
488
489 static int handle_msg_handling;
490
491 void setup_z180_serv(void)
492 {
493
494 handle_msg_handling = bg_register(msg_handling, 0);
495 }
496
497 void restart_z180_serv(void)
498 {
499 z80_bus_cmd(Request);
500 z80_write(0x40, 0);
501 z80_write(0x41, 0);
502 z80_write(0x42, 0);
503 z80_bus_cmd(Release);
504
505 for (int i = 0; i < NUM_FIFOS; i++)
506 z80_memfifo_init(i, 0);
507 bg_setstat(handle_msg_handling, 0);
508
509 }
510
511 /*--------------------------------------------------------------------------*/
512
513 const FLASH uint8_t iniprog[] = {
514 0xAF, // xor a
515 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
516 0x3E, 0x30, // ld a,030h
517 0xED, 0x39, 0x32 //out0 (dcntl),a ;0 mem, max i/0 wait states
518 };
519
520 const FLASH uint8_t sertest[] = {
521 0xAF, // xor a
522 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
523 0x3E, 0x30, // ld a,030h
524 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
525 0x3E, 0x80, // ld a,M_MPBT ;no MP, PS=10, DR=16, SS=0
526 0xED, 0x39, 0x03, // out0 (cntlb1),a
527 0x3E, 0x64, // ld a,M_RE + M_TE + M_MOD2 ;
528 0xED, 0x39, 0x01, // out0 (cntla1),a
529 0x3E, 0x00, // ld a,0
530 0xED, 0x39, 0x05, // out0 (stat1),a ;Enable rx interrupts
531 0xED, 0x38, 0x05, //l0:in0 a,(stat1)
532 0xE6, 0x80, // and 80h
533 0x28, 0xF9, // jr z,l0
534 0xED, 0x00, 0x09, // in0 b,(rdr1)
535 0xED, 0x38, 0x05, //l1:in0 a,(stat1)
536 0xE6, 0x02, // and 02h
537 0x28, 0xF9, // jr z,l1
538 0xED, 0x01, 0x07, // out0 (tdr1),b
539 0x18, 0xEA, // jr l0
540 };
541
542 const FLASH uint8_t test1[] = {
543 0xAF, // xor a
544 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
545 0x3E, 0x30, // ld a,030h
546 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
547 0x21, 0x1E, 0x00, // ld hl,dmclrt ;load DMA registers
548 0x06, 0x08, // ld b,dmct_e-dmclrt
549 0x0E, 0x20, // ld c,sar0l
550 0xED, 0x93, // otimr
551 0x3E, 0xC3, // ld a,0c3h ;dst +1, src +1, burst
552 0xED, 0x39, 0x31, // out0 (dmode),a ;
553 0x3E, 0x62, // ld a,062h ;enable dma0,
554 0xED, 0x39, 0x30, //cl_1: out0 (dstat),a ;copy 64k
555 0x18, 0xFB, // jr cl_1 ;
556 0x00, 0x00, //dmclrt: dw 0 ;src (inc)
557 0x00, // db 0 ;src
558 0x00, 0x00, // dw 0 ;dst (inc),
559 0x00, // db 0 ;dst
560 0x00, 0x00, // dw 0 ;count (64k)
561 };