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[z180-stamp.git] / avr / z80-if.c
1 /*
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /**
8 *
9 * Pin assignments
10 *
11 * | Z180-Sig | AVR-Port | Dir | Special Function |
12 * +------------+---------------+-------+-----------------------+
13 * | A0 | PA 0 | O | |
14 * | A1 | PA 1 | O | |
15 * | A2 | PA 2 | O | |
16 * | A3 | PA 3 | O | |
17 * | A4 | PA 4 | O | |
18 * | A5 | PA 5 | O | |
19 * | A6 | PA 6 | O | |
20 * | A7 | PA 7 | O | |
21 * | A8 | PC 0 | O | |
22 * | A9 | PC 1 | O | |
23 * | A10 | PC 2 | O | |
24 * | A11 | PC 3 | O | |
25 * | A12 | PC 4 | O | |
26 * | A13 | PC 5 | O | |
27 * | A14 | PC 6 | O | |
28 * | A15 | PC 7 | O | |
29 * | A16 | PE 2 | O | |
30 * | A17 | PE 3 | O | |
31 * | A18 | PE 4 | O | |
32 * | D0 | PF 0 | I/O | |
33 * | D1 | PF 1 | I/O | |
34 * | D2 | PF 2 | I/O | |
35 * | D3 | PF 3 | I/O | |
36 * | D4 | PF 4 | I/O | |
37 * | D5 | PF 5 | I/O | |
38 * | D6 | PF 6 | I/O | |
39 * | D7 | PF 7 | I/O | |
40 * | RD | PD 3 | O | |
41 * | WR | PD 2 | O | |
42 * | MREQ | PD 4 | O | |
43 * | RST | PD 5 | O | |
44 * | BUSREQ | PD 7 | O | |
45 * | BUSACK | PD 6 | I | |
46 * | IOCS1 | PE 5 | I | |
47 * |* HALT | P | | |
48 * |* NMI | P | | |
49 * | | P | | |
50 * | | P | | af1 USART1_TX |
51 * | | P | | af1 USART1_RX |
52 * | | P |JTDI | remap SPI1_NSS' |
53 * | | P |JTDO | remap SPI1_SCK' |
54 * | | P |JTRST | remap SPI1_MISO' |
55 * | | P | | remap SPI1_MOSI' |
56 * | | P | | af1 OSC32 |
57 * | | P | | af1 OSC32 |
58
59 */
60
61
62 #include "common.h"
63 #include <util/atomic.h>
64 #include "debug.h"
65 #include "z80-if.h"
66
67
68
69 //#define P_ZCLK PORTB
70 //#define ZCLK 5
71 //#define DDR_ZCLK DDRB
72 #define P_MREQ PORTD
73 #define MREQ 4
74 #define DDR_MREQ DDRD
75 #define P_RD PORTD
76 #define RD 3
77 #define P_WR PORTD
78 #define WR 2
79 #define P_BUSREQ PORTD
80 #define BUSREQ 7
81 #define DDR_BUSREQ DDRD
82 #define P_BUSACK PORTD
83 #define PIN_BUSACK PIND
84 #define BUSACK 6
85 #define DDR_BUSACK DDRD
86 //#define P_HALT PORTA
87 //#define HALT 12
88 #define P_IOCS1 PORTE
89 #define IOCS1 5
90 #define DDR_IOCS1 DDRE
91 //#define P_NMI PORTB
92 //#define NMI 7
93 #define P_RST PORTD
94 #define DDR_RST DDRD
95 #define RST 5
96
97
98 #define P_DB PORTF
99 #define PIN_DB PINF
100 #define DDR_DB DDRF
101
102 #define P_ADL PORTA
103 #define P_ADH PORTC
104 #define P_ADB PORTE
105 #define PIN_ADB PINE
106 #define DDR_ADL DDRA
107 #define DDR_ADH DDRC
108 #define DDR_ADB DDRE
109
110 #define ADB_WIDTH 3
111 #define ADB_SHIFT 2
112 //#define ADB_PORT PORTE
113
114
115 //#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
116 #define Z80_O_MREQ SBIT(P_MREQ, 4)
117 #define Z80_O_RD SBIT(P_RD, 3)
118 #define Z80_O_WR SBIT(P_WR, 2)
119 #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
120 //#define Z80_O_NMI SBIT(P_NMI, )
121 #define Z80_O_RST SBIT(P_RST, 5)
122 #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
123 //#define Z80_I_HALT SBIT(P_HALT, )
124
125
126 #define BUS_TO 20
127
128
129 #define MASK(n) ((1<<(n))-1)
130 #define SMASK(w,s) (MASK(w) << (s))
131
132
133 typedef union {
134 uint32_t l;
135 uint16_t w[2];
136 uint8_t b[4];
137 } addr_t;
138
139
140 static zstate_t zstate;
141 static volatile uint8_t timer; /* used for bus timeout */
142
143 /*---------------------------------------------------------*/
144 /* 10Hz timer interrupt generated by OC4A */
145 /*---------------------------------------------------------*/
146
147 ISR(TIMER4_COMPA_vect)
148 {
149
150 uint8_t i = timer;
151
152 if (i)
153 timer = i - 1;
154 }
155
156 /*--------------------------------------------------------------------------*/
157
158
159 static void z80_addrbus_set_tristate(void)
160 {
161 /* /MREQ, /RD, /WR: Input, no pullup */
162 DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
163 Z80_O_MREQ = 0;
164 Z80_O_RD = 0;
165 Z80_O_WR = 0;
166
167 P_ADL = 0;
168 DDR_ADL = 0;
169 P_ADH = 0;
170 DDR_ADH = 0;
171 PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
172 DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
173 }
174
175
176 static void z80_addrbus_set_active(void)
177 {
178 /* /MREQ, /RD, /WR: Output and high */
179 Z80_O_MREQ = 1;
180 Z80_O_RD = 1;
181 Z80_O_WR = 1;
182 DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);
183
184 DDR_ADL = 0xff;
185 DDR_ADH = 0xff;
186 DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
187 }
188
189
190 static void z80_dbus_set_in(void)
191 {
192 DDR_DB = 0;
193 P_DB = 0;
194 }
195
196
197 static void z80_dbus_set_out(void)
198 {
199 DDR_DB = 0xff;
200 }
201
202
203 static void z80_reset_pulse(void)
204 {
205 Z80_O_RST = 0;
206 _delay_us(10);
207 Z80_O_RST = 1;
208 }
209
210
211 void z80_setup_bus(void)
212 {
213 /* /ZRESET: Output and low */
214 Z80_O_RST = 0;
215 DDR_RST |= _BV(RST);
216
217 /* /BUSREQ: Output and high */
218 Z80_O_BUSREQ = 1;
219 DDR_BUSREQ |= _BV(BUSREQ);
220
221 /* /BUSACK: Input, no pullup */
222 DDR_BUSACK &= ~_BV(BUSACK);
223 P_BUSACK &= ~_BV(BUSACK);
224
225 /* /IOCS1: Input, no pullup */
226 DDR_IOCS1 &= ~_BV(IOCS1);
227 P_IOCS1 &= ~_BV(IOCS1);
228
229 z80_addrbus_set_tristate();
230 z80_dbus_set_in();
231
232 zstate = RESET;
233
234 /* Timer 4 */
235 PRR1 &= ~_BV(PRTIM4);
236 OCR4A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
237 TCCR4B = (0b01<<WGM42)|(0b101<<CS30); /* CTC Mode, Prescaler 1024 */
238 TIMSK4 = _BV(OCIE4A); /* Enable oca interrupt */
239
240 }
241
242
243 zstate_t z80_bus_state(void)
244 {
245 return zstate;
246 }
247
248
249 static void z80_busreq_hpulse(void)
250 {
251 z80_dbus_set_in();
252 z80_addrbus_set_tristate();
253
254 ATOMIC_BLOCK(ATOMIC_FORCEON) {
255 Z80_O_BUSREQ = 1;
256 Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
257 Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
258 }
259
260 if (zstate & ZST_ACQUIRED) {
261 timer = BUS_TO;
262 while (Z80_I_BUSACK == 1 && timer)
263 ;
264 if (Z80_I_BUSACK == 0)
265 z80_addrbus_set_active();
266 }
267 }
268
269
270 /*
271
272 + | | | | |
273 + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
274 + | | | | |
275 + | 0 | 1 | 2 | 3 |
276 Event + | | | | |
277 ----------------+---------------+---------------+---------------+---------------+
278 | | | | |
279 Reset | 0 | 0 | 0 | 0 |
280 | | | | |
281 | | | | |
282 Request | 1 | | 3 | |
283 | | | | |
284 | | | | |
285 Release | | 0 | | 2 |
286 | | | | |
287 | | | | |
288 Run | 2 | 3 | | |
289 | | | | |
290 | | | | |
291 Restart | | | 2 | 3 |
292 | | | | |
293 | | | | |
294 M_Cycle | | | | 3 |
295 | | | | |
296 | | | | |
297 */
298
299 zstate_t z80_bus_cmd(bus_cmd_t cmd)
300 {
301 switch (cmd) {
302
303 case Reset:
304 z80_dbus_set_in();
305 z80_addrbus_set_tristate();
306 Z80_O_RST = 0;
307 Z80_O_BUSREQ = 1;
308 zstate = RESET;
309 break;
310
311 case Request:
312 switch (zstate) {
313 case RESET:
314 Z80_O_BUSREQ = 0;
315 Z80_O_RST = 1;
316 timer = BUS_TO;
317 while (Z80_I_BUSACK == 1 && timer)
318 ;
319 if (Z80_I_BUSACK == 0) {
320 z80_addrbus_set_active();
321 zstate = RESET_AQRD;
322 } else {
323 Z80_O_RST = 0;
324 Z80_O_BUSREQ = 1;
325 }
326 break;
327
328 case RUNNING:
329 Z80_O_BUSREQ = 0;
330 timer = BUS_TO;
331 while (Z80_I_BUSACK == 1 && timer)
332 ;
333 if (Z80_I_BUSACK == 0) {
334 z80_addrbus_set_active();
335 zstate = RUNNING_AQRD;
336 } else {
337 Z80_O_BUSREQ = 1;
338 }
339 break;
340
341 default:
342 break;
343 }
344 break;
345
346 case Release:
347 switch (zstate) {
348 case RESET_AQRD:
349 z80_dbus_set_in();
350 z80_addrbus_set_tristate();
351 Z80_O_RST = 0;
352 Z80_O_BUSREQ = 1;
353 zstate = RESET;
354 break;
355 case RUNNING_AQRD:
356 z80_dbus_set_in();
357 z80_addrbus_set_tristate();
358 Z80_O_BUSREQ = 1;
359 zstate = RUNNING;
360 break;
361 default:
362 break;
363 }
364 break;
365
366 case Run:
367 switch (zstate) {
368 case RESET:
369 Z80_O_RST = 1;
370 zstate = RUNNING;
371 break;
372
373 case RESET_AQRD:
374 z80_dbus_set_in();
375 z80_addrbus_set_tristate();
376 z80_reset_pulse();
377 z80_addrbus_set_active();
378 zstate = RUNNING_AQRD;
379 break;
380 default:
381 break;
382 }
383 break;
384
385 case Restart:
386 switch (zstate) {
387 case RUNNING:
388 case RUNNING_AQRD:
389 z80_reset_pulse();
390 break;
391 default:
392 break;
393 }
394 break;
395
396 case M_Cycle:
397 switch (zstate) {
398 case RUNNING_AQRD:
399 z80_busreq_hpulse(); /* TODO: */
400 break;
401 default:
402 break;
403 }
404 }
405 return zstate;
406 }
407
408
409 /*--------------------------------------------------------------------------*/
410
411 static
412 //inline __attribute__ ((always_inline))
413 void z80_setaddress(uint32_t addr)
414 {
415 addr_t x; x.l = addr;
416
417 P_ADL = x.b[0];
418 P_ADH = x.b[1];
419 PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
420 }
421
422 void z80_write(uint32_t addr, uint8_t data)
423 {
424 z80_setaddress(addr);
425 Z80_O_MREQ = 0;
426 z80_dbus_set_out();
427 P_DB = data;
428 P_DB = data;
429 Z80_O_WR = 0;
430 Z80_O_WR = 0;
431 Z80_O_WR = 1;
432 Z80_O_MREQ = 1;
433 }
434
435 uint8_t z80_read(uint32_t addr)
436 {
437 uint8_t data;
438
439 z80_setaddress(addr);
440 Z80_O_MREQ = 0;
441 z80_dbus_set_in();
442 Z80_O_RD = 0;
443 Z80_O_RD = 0;
444 Z80_O_RD = 0;
445 data = PIN_DB;
446 Z80_O_RD = 1;
447 Z80_O_MREQ = 1;
448
449 return data;
450 }
451
452
453 void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
454 {
455 z80_dbus_set_out();
456 Z80_O_MREQ = 0;
457 P_DB = data;
458 while(length--) {
459 z80_setaddress(addr++);
460 Z80_O_WR = 0;
461 Z80_O_WR = 0;
462 Z80_O_WR = 1;
463 }
464 Z80_O_MREQ = 1;
465 }
466
467 void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
468 {
469 uint8_t data;
470
471 z80_dbus_set_out();
472 Z80_O_MREQ = 0;
473 while(length--) {
474 z80_setaddress(dest++);
475 data = *src++;
476 P_DB = data;
477 P_DB = data;
478 Z80_O_WR = 0;
479 Z80_O_WR = 0;
480 Z80_O_WR = 1;
481 }
482 Z80_O_MREQ = 1;
483 }
484
485 void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
486 {
487 uint8_t data;
488
489 z80_dbus_set_out();
490 Z80_O_MREQ = 0;
491 while(length--) {
492 z80_setaddress(dest++);
493 data = *src++;
494 P_DB = data;
495 P_DB = data;
496 Z80_O_WR = 0;
497 Z80_O_WR = 0;
498 Z80_O_WR = 1;
499 }
500 Z80_O_MREQ = 1;
501 }
502
503 void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
504 {
505 uint8_t data;
506
507 Z80_O_MREQ = 0;
508 z80_dbus_set_in();
509 while(length--) {
510 z80_setaddress(src++);
511 Z80_O_RD = 0;
512 Z80_O_RD = 0;
513 Z80_O_RD = 0;
514 data = PIN_DB;
515 Z80_O_RD = 1;
516 *dest++ = data;
517 }
518 Z80_O_MREQ = 1;
519 }
520
521
522 /*
523 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
524 017A' rx.in_idx: ds 1 ;
525 017B' rx.out_idx: ds 1 ;
526 017C' rx.buf: ds rx.buf_len ;
527 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
528
529 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
530 018D' tx.in_idx: ds 1 ;
531 018E' tx.out_idx: ds 1 ;
532 018F' tx.buf: ds tx.buf_len ;
533 019E' tx.buf_end equ $-1 ; last byte
534 */
535
536
537 typedef struct __attribute__((packed)) {
538 uint8_t mask;
539 uint8_t in_idx;
540 uint8_t out_idx;
541 uint8_t buf[];
542 } zfifo_t;
543
544
545
546 #define FIFO_BUFSIZE_MASK -3
547 #define FIFO_INDEX_IN -2
548 #define FIFO_INDEX_OUT -1
549
550
551 static struct {
552 uint32_t base;
553 uint8_t idx_out,
554 idx_in,
555 mask;
556 } fifo_dsc[NUM_FIFOS];
557
558
559 void z80_memfifo_init(const fifo_t f, uint32_t addr)
560 {
561 fifo_dsc[f].base = addr;
562
563 if (addr != 0) {
564
565 DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
566
567 z80_bus_cmd(Request);
568 fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
569 fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
570 fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
571 z80_bus_cmd(Release);
572 }
573 }
574
575
576 int z80_memfifo_is_empty(const fifo_t f)
577 {
578 int rc = 1;
579
580 if (fifo_dsc[f].base != 0) {
581
582 uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
583 uint8_t idx;
584
585 z80_bus_cmd(Request);
586 idx = z80_read(adr);
587 z80_bus_cmd(Release);
588 rc = idx == fifo_dsc[f].idx_out;
589 }
590
591 return rc;
592 }
593
594 int z80_memfifo_is_full(const fifo_t f)
595 {
596 int rc = 0;
597
598 if (fifo_dsc[f].base != 0) {
599 z80_bus_cmd(Request);
600 rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
601 == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
602 z80_bus_cmd(Release);
603 }
604 return rc;
605 }
606
607
608 uint8_t z80_memfifo_getc_wait(const fifo_t f)
609 {
610 uint8_t rc, idx;
611
612 while (z80_memfifo_is_empty(f))
613 ;
614
615 z80_bus_cmd(Request);
616 idx = fifo_dsc[f].idx_out;
617 rc = z80_read(fifo_dsc[f].base+idx);
618 fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
619 z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
620 z80_bus_cmd(Release);
621
622 return rc;
623 }
624
625 int z80_memfifo_getc(const fifo_t f)
626 {
627 int rc = -1;
628
629 if (fifo_dsc[f].base != 0) {
630 uint8_t idx = fifo_dsc[f].idx_out;
631 z80_bus_cmd(Request);
632 if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
633 rc = z80_read(fifo_dsc[f].base+idx);
634 fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
635 z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
636 }
637 z80_bus_cmd(Release);
638 }
639
640 return rc;
641 }
642
643
644 void z80_memfifo_putc(fifo_t f, uint8_t val)
645 {
646 int idx;
647
648 while (z80_memfifo_is_full(f))
649 ;
650
651 z80_bus_cmd(Request);
652 idx = fifo_dsc[f].idx_in;
653 z80_write(fifo_dsc[f].base+idx, val);
654 fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
655 z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
656 z80_bus_cmd(Release);
657 }
Z180 Stamp Monitor