z180/config.inc

   1
   2 FALSE   equ     0
   3 TRUE    equ     NOT FALSE
   4
   5 banked  equ     true
   6
   7 ;-----------------------------------------------------
   8 ; CPU and BANKING types
   9
  10
  11 CPU_Z180        equ     TRUE
  12 CPU_Z80         equ     FALSE
  13
  14 ROMSYS          equ     FALSE
  15
  16 AVRCLK          equ     18432           ;[KHz]
  17
  18     if CPU_Z180
  19
  20 ;-----------------------------------------------------
  21 FOSC            equ     AVRCLK/2        ;Oscillator frequency [KHz]
  22 PHI             equ     FOSC*2          ;CPU frequency (clock doubler enabled)
  23
  24 ;-----------------------------------------------------
  25 ; Programmable Reload Timer (PRT)
  26
  27 PRT_PRE         equ     20              ;PRT prescaler
  28
  29 ; Reload value for 10 ms Int. (0.1KHz):
  30 ; tc10ms = phi/prescale/0.1KHz  = phi / (prescale/10)
  31
  32 PRT_TC10MS      equ     PHI / (PRT_PRE/10)
  33
  34 ;-----------------------------------------------------
  35 ; MMU
  36
  37 COMMON_SIZE     equ     16*1024         ;Common Area size in bytes
  38                                         ;must be multiple of 4K
  39
  40 if (COMMON_SIZE mod 1000h)
  41         .printx COMMON_SIZE not multiple of 4K!
  42         end     ;stop assembly
  43 endif
  44
  45 CSK     equ     COMMON_SIZE/1000h       ;
  46 CA      equ     10h - CSK               ;common area start
  47 BA      equ     0                       ;banked area start
  48
  49 SYS$CBR         equ     0
  50 SYS$CBAR        equ     CA*16 + CA      ;CBAR in system mode
  51 USR$CBAR        equ     CA*16 + BA      ;CBAR in user mode (CP/M)
  52
  53
  54 BANKS           equ     18              ;max nr. of banks
  55
  56 ;-----------------------------------------------------
  57
  58 CREFSH          equ     0               ;Refresh rate register (disable refresh)
  59 CWAITIO         equ     3 shl IWI0      ;Max I/O Wait States, 0 Memory Wait States
  60 PHI_X2          equ     0               ;set to M_X2CM to enable the clock doubler
  61
  62     endif               ;CPU_Z180
  63     if  CPU_Z80
  64
  65 PHI             equ     AVRCLK/5        ;CPU frequency [KHz]
  66 BAUDCLCK        equ     AVRCLK/10       ;Baudrate clock [KHz]
  67 ;BDCLK16                equ
  68
  69 SIOAD   EQU     0bch
  70 SIOAC   EQU     0bdh
  71 SIOBD   EQU     0beh
  72 SIOBC   EQU     0bfh
  73
  74 CTC0    EQU     0f4h
  75 CTC1    EQU     0f5h
  76 CTC2    EQU     0f6h
  77 CTC3    EQU     0f7h
  78
  79 ;
  80 ; Init Serial I/O for console input and output (SIO-A)
  81 ;
  82 ; Baudrate clock: 1843200 Hz (Bus connector pin A17)
  83 ;
  84 ; Baudrate   Divider    SIO     CTC
  85 ; ---------------------------------
  86 ; 115200          16     16       1
  87 ;  57600          32     16       2
  88 ;  38400          48     16       3
  89 ;  19200          96     16       6
  90 ;   9600         192     16      12
  91 ;   4800         384     16      24
  92 ;   2400         768     16      48
  93 ;   1200        1536     16      96
  94 ;    600        3072     16     192
  95 ;    300        6144     64      92
  96
  97     endif       ; CPU_Z80
  98
  99     if  ROMSYS
 100 c$rom           equ     0a5h
 101 ROM_EN          equ     0C0h
 102 ROM_DIS         equ     ROMEN+1
 103      if CPU_Z180
 104 CWAITROM        equ     2 shl MWI0
 105      endif
 106     endif
 107
 108
 109 DDTZRSTVEC      equ     030h            ;DDTZ Restart vector (breakpoints)
 110
 111 INIDONE         equ     03Fh            ;CP/M skip hw init, if this address
 112 INIDONEVAL      equ     080h            ;    is set to this value.
 113
 114 mtx.fifo_len    equ     32              ;Message transfer fifos
 115 mtx.fifo_id     equ     0               ;    This *must* have #0
 116 mrx.fifo_len    equ     32
 117 mrx.fifo_id     equ     1
 118
 119 ci.fifo_len     equ     32              ;AVRCON Character I/O via AVR
 120 ci.fifo_id      equ     2
 121 co.fifo_len     equ     32
 122 co.fifo_id      equ     3
 123
 124 s1.rx_len       equ     128             ;Serial 1 (ASCI1) buffers
 125 s1.rx_id        equ     4               ;
 126 s1.tx_len       equ     128             ;
 127 s1.tx_id        equ     5               ;
 128
 129 AVRINT5         equ     4Fh
 130 AVRINT6         equ     5Fh
 131 ;PMSG           equ     80h
 132
 133 ;-----------------------------------------------------
 134 ; Definition of (logical) top 2 memory pages
 135
 136 sysram_start    equ     0FE00h
 137 stacksize       equ     80
 138
 139 isvsw_loc       equ     0FEE0h
 140
 141 ivtab           equ     0ffc0h          ;int vector table
 142 iv2tab          equ     ivtab + 2*9
 143
 144
 145
 146 ;-----------------------------------------------------
 147
 148 o.id            equ     -4
 149 o.mask          equ     -3
 150 o.in_idx        equ     -2
 151 o.out_idx       equ     -1
 152
 153         .lall
 154
 155 mkbuf   macro   id,name,size
 156   if ((size AND (size-1)) NE 0) OR (size GT 256)
 157     .printx Error: buffer ^size must be power of 2 and in range 0..256!
 158     name&.mask equ ;wrong size error
 159   else
 160     db id
 161     ds 3
 162     name:: ds size
 163     name&.mask equ low (size-1)
 164     if size ne 0
 165       name&.end equ $-1
 166       name&.len equ size
 167       name&.id equ id
 168     endif
 169   endif
 170 endm
 171
 172 ;-----------------------------------------------------
 173
 174 inidat  macro
 175         cseg
 176 ??ps.a  defl    $
 177         endm
 178
 179 inidate macro
 180 ??ps.len defl   $ - ??ps.a
 181         dseg
 182         ds      ??ps.len
 183         endm