*/
#include <avr/io.h>
-#include <util/delay.h>
#include <util/atomic.h>
#include <stdio.h>
#include "debug.h"
/* Number of array elements */
#define NELEMS(x) (sizeof x/sizeof *x)
-
-#define CONCAT(x,y) x ## y
-#define EVALUATOR(x,y) CONCAT(x,y)
-
-#define GPIO_(X) CONCAT(GPIO, X)
-
struct bits {
uint8_t b0:1;
uint8_t b1:1;
uint8_t b7:1;
} __attribute__((__packed__));
+typedef struct bits pbit_t;
+
#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
-#define P_ZCLK PORTB
-#define ZCLK 7
-#define DDR_ZCLK DDRB
+//#define P_ZCLK PORTB
+//#define ZCLK 5
+//#define DDR_ZCLK DDRB
#define P_MREQ PORTD
#define MREQ 4
#define DDR_MREQ DDRD
//#define ADB_PORT PORTE
-#define Z80_O_ZCLK SBIT(P_ZCLK, 7)
+//#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
#define Z80_O_MREQ SBIT(P_MREQ, 4)
#define Z80_O_RD SBIT(P_RD, 3)
#define Z80_O_WR SBIT(P_WR, 2)
#define MASK(n) ((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))
-#define LOWSPEED 50000
-
typedef union {
uint32_t l;
/*--------------------------------------------------------------------------*/
-static
-uint8_t is_lowspeed()
-{
- return (TCCR1B & 7) < 2 &&
- OCR1A > (F_CPU / 2 / LOWSPEED);
-}
-
-static
-void z80_setup_clock(void)
-{
- /* ZCLK: Output and low */
- DDR_ZCLK |= _BV(ZCLK);
- Z80_O_ZCLK = 0;
-
- DDRB |= _BV(6); /* Debug */
- PORTB |= _BV(6); /* Debug */
-
- PRR0 &= ~_BV(PRTIM1);
-
- /* Timer1: CTC: Toggle OC1C on compare match */
- OCR1A = 0;
- OCR1C = 0;
- TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10);
- TCCR1B = (0b01 << WGM12) | (0b001 << CS10);
-}
-
-
-int z80_clock_set(unsigned long freq)
-{
- unsigned long ocrval = F_CPU / freq / 2;
- uint8_t prescale = 0;
-
- while (ocrval > (1L<<16)) {
- prescale++;
- if (prescale < 3)
- ocrval = ocrval / 8;
- else
- ocrval = ocrval / 4;
- }
-
- if ((ocrval == 0) || (prescale > 4))
- return -1;
-
- ocrval -= 1;
-
- PINB |= _BV(6); /* Debug */
-
- /* Stop Timer */
- TCCR1B = (0b01 << WGM12) | (0b000 << CS10);
- TCNT1 = 0;
-
- OCR1A = ocrval;
- OCR1CL = ocrval;
- TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10);
- TCCR1B = (0b01 << WGM12) | ((prescale+1) << CS10);
-
- if (ocrval == 0)
- ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
- TCNT1 = 0xFFFF;
- }
-
- PINB |= _BV(6); /* Debug */
-
- return 0;
-}
-
-uint32_t z80_clock_get(void)
-{
- uint32_t count = (OCR1A + 1L) * 2;
- uint8_t pre = (TCCR1B & 7) - 1;
-
- while (pre) {
- if (pre > 2)
- count *= 4;
- else
- count *= 8;
- pre--;
- }
-
- return F_CPU/count;
-}
-
-
static void z80_addrbus_set_tristate(void)
{
void z80_setup_bus(void)
{
- z80_setup_clock();
-
/* /ZRESET: Output and low */
Z80_O_RST = 0;
DDR_RST |= _BV(RST);
z80_dbus_set_in();
z80_addrbus_set_tristate();
- ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
Z80_O_BUSREQ = 1;
Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
} fifo_dsc[NUM_FIFOS];
-void z80_memfifo_init(const fifo_t f, uint32_t adr)
+void z80_memfifo_init(const fifo_t f, uint32_t addr)
{
+ fifo_dsc[f].base = addr;
-DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr);
+ if (addr != 0) {
- fifo_dsc[f].base = adr;
+DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
- z80_bus_cmd(Request);
-
- fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
- fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
- fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);
-
- z80_bus_cmd(Release);
+ z80_bus_cmd(Request);
+ fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
+ fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
+ fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
+ z80_bus_cmd(Release);
+ }
}
return rc;
}
-uint8_t z80_memfifo_getc(const fifo_t f)
+
+uint8_t z80_memfifo_getc_wait(const fifo_t f)
{
uint8_t rc, idx;
return rc;
}
+int z80_memfifo_getc(const fifo_t f)
+{
+ int rc = -1;
+
+ if (fifo_dsc[f].base != 0) {
+ uint8_t idx = fifo_dsc[f].idx_out;
+ z80_bus_cmd(Request);
+ if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
+ rc = z80_read(fifo_dsc[f].base+idx);
+ fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
+ z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
+ }
+ z80_bus_cmd(Release);
+ }
+
+ return rc;
+}
+
void z80_memfifo_putc(fifo_t f, uint8_t val)
{
z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
z80_bus_cmd(Release);
}
-
-/*--------------------------------------------------------------------------*/
-/*
- TODO: Rewrite msg_fifo routines for AVR
-*/
-
-static struct {
- uint32_t base;
- //uint8_t idx_out, idx_in;
- uint16_t count;
- uint8_t buf[256];
- } msg_fifo;
-
-/*--------------------------------------------------------------------------*/
-
-#if 0
-
-static void tim1_setup(void)
-{
- RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
- RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
-
- TIM1_CR1 = 0;
-
- TIM1_SMCR = 0
- /* | TIM_SMCR_ETP */
- /* | TIM_SMCR_ETF_CK_INT_N_2 */
- | TIM_SMCR_TS_ETRF
- | TIM_SMCR_SMS_OFF
- ;
-
- TIM1_DIER = TIM_DIER_TDE;
-
-
- TIM1_CCMR1 = 0
- | TIM_CCMR1_OC1M_FORCE_LOW
- | TIM_CCMR1_CC1S_OUT;
-
- TIM1_SMCR |= TIM_SMCR_SMS_TM;
-}
-
-#endif
-
-/*--------------------------------------------------------------------------*/
-
-void z80_setup_msg_fifo(void)
-{
-// gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
-// GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);
-
-//...
-
-// msg_fifo.count = NELEMS(msg_fifo.buf);
- msg_fifo.count = 0;
- msg_fifo.base = 0;
-
-}
-
-
-void z80_init_msg_fifo(uint32_t addr)
-{
-
-DBG_P(1, "z80_init_msg_fifo: %lx\n", addr);
-
- z80_bus_cmd(Request);
- z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN));
- z80_bus_cmd(Release);
- msg_fifo.base = addr;
-}
-
-
-int z80_msg_fifo_getc(void)
-{
- int c = -1;
-
-#if 0
- if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) {
- c = msg_fifo.buf[msg_fifo.count];
- if (++msg_fifo.count == NELEMS(msg_fifo.buf))
- msg_fifo.count = 0;
-
- if (msg_fifo.base != 0) {
- z80_bus_cmd(Request);
- z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count);
- z80_bus_cmd(Release);
- }
- }
-#endif
-
- return c;
-}
projects / z180-stamp.git / blobdiff