+SYS$CBR equ BNK_SIZE\r
+SYS$CBAR equ CA*16 + CA ;CBAR in system mode\r
+USR$CBAR equ CA*16 + BA ;CBAR in user mode (CP/M)\r
+\r
+ endif\r
+\r
+\r
+;-----------------------------------------------------\r
+\r
+CREFSH equ 0 ;Refresh rate register (disable refresh)\r
+CWAITIO equ 3 shl IWI0 ;Max I/O Wait States, 0 Memory Wait States\r
+PHI_X2 equ 0 ;set to M_X2CM to enable the clock doubler\r
+\r
+ endif ;CPU_Z180\r
+ if CPU_Z80\r
+\r
+PHI equ AVRCLK/5 ;CPU frequency [KHz]\r
+BAUDCLCK equ AVRCLK/10 ;Baudrate clock [KHz]\r
+;BDCLK16 equ\r
+\r
+SIOAD EQU 0bch\r
+SIOAC EQU 0bdh\r
+SIOBD EQU 0beh\r
+SIOBC EQU 0bfh\r
+\r
+CTC0 EQU 0f4h\r
+CTC1 EQU 0f5h\r
+CTC2 EQU 0f6h\r
+CTC3 EQU 0f7h\r
+\r
+;\r
+; Init Serial I/O for console input and output (SIO-A)\r
+;\r
+; Baudrate clock: 1843200 Hz (Bus connector pin A17)\r
+;\r
+; Baudrate Divider SIO CTC\r
+; ---------------------------------\r
+; 115200 16 16 1\r
+; 57600 32 16 2\r
+; 38400 48 16 3\r
+; 19200 96 16 6\r
+; 9600 192 16 12\r
+; 4800 384 16 24\r
+; 2400 768 16 48\r
+; 1200 1536 16 96\r
+; 600 3072 16 192\r
+; 300 6144 64 92\r
+\r
+ endif ; CPU_Z80\r
+\r
+ if ROMSYS\r