b2m MPBR, 3 ;Multiprocessor Bit Receive (Read)\r
b2m EFR, 3 ;Error Flag Reset (Write)\r
b2m MOD2, 2 ;Data Format Mode 1 = 8-Bit data\r
- b2m NOD1, 1 ;1 = Parity enabled\r
+ b2m MOD1, 1 ;1 = Parity enabled\r
b2m MOD0, 0 ;1 = 2 stop bits\r
\r
cntlb0 equ IOBASE+02h ;ASCI Control Register B Channel 0\r
b2m FE,4 ;Framing Error\r
b2m RIE,3 ;Receive Interrupt Enable\r
b2m DCD0,2 ;Data Carrier Detect (Ch 0)\r
- b2m CTS1E,2 ;Clear To Send (Ch 1)\r
+ b2m CTS1E,2 ;Clear To Send Enable (Ch 1)\r
b2m TDRE,1 ;Transmit Data Register Empty\r
b2m TIE,0 ;Transmit Interrupt Enable\r
\r
\r
asext0 equ IOBASE+12h ;ASCI Extension Control Register\r
asext1 equ IOBASE+13h ;ASCI Extension Control Register\r
+ b2m DCD0DIS,6 ;DCD0 Disable\r
+ b2m CTS0DIS,5 ;CTS0 Disable\r
+ b2m X1,4 ;CKA * 1 Clock/Samle Rate Divider\r
+ b2m BRGMOD,3 ;BRG Mode (Baud rate generator)\r
+ b2m BREAKEN,2 ;Break Enable\r
+ b2m BREAK,1 ;Break detected\r
+ b2m SENDBREAK,0 ;Send Break\r
\r
tmdr1l equ IOBASE+14h ;Timer Data Register Channel 1\r
tmdr1h equ IOBASE+15h ;\r
dstat equ IOBASE+30h ;DMA Status Register\r
b2m DE1,7 ;DMA enable ch 1,0\r
b2m DE0,6 ;\r
- b2m DWE1,5 ;DMA Enable Bit Write Enable 1,0\r
- b2m DWE0,4 ;\r
+ b2m NDWE1,5 ;DMA Enable Bit Write Enable 1,0\r
+ b2m NDWE0,4 ;\r
b2m DIE1,3 ;DMA Interrupt Enable 1,0\r
b2m DIE0,2 ;\r
b2m DME,0 ;DMA Master enable\r
IV$ASCI1 equ 16 ;ASCI channel 1 (lowest priority)\r
\r
.list\r
-\r