*
* Pin assignments
*
- * | Z180-Sig | AVR-Port | Dir | Special Function |
+ * | Z180-Sig | AVR-Port | Dir | Special Function |
* +------------+---------------+-------+-----------------------+
* | A0 | PA 0 | O | |
* | A1 | PA 1 | O | |
*/
#include <avr/io.h>
-#include <util/delay.h>
+#include <util/atomic.h>
#include <stdio.h>
#include "debug.h"
#include "z80-if.h"
/* Number of array elements */
#define NELEMS(x) (sizeof x/sizeof *x)
-
-#define CONCAT(x,y) x ## y
-#define EVALUATOR(x,y) CONCAT(x,y)
-
-#define GPIO_(X) CONCAT(GPIO, X)
-
struct bits {
uint8_t b0:1;
uint8_t b1:1;
uint8_t b7:1;
} __attribute__((__packed__));
-#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
+typedef struct bits pbit_t;
+#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
+//#define P_ZCLK PORTB
+//#define ZCLK 5
+//#define DDR_ZCLK DDRB
#define P_MREQ PORTD
#define MREQ 4
#define DDR_MREQ DDRD
#define BUSREQ 7
#define DDR_BUSREQ DDRD
#define P_BUSACK PORTD
+#define PIN_BUSACK PIND
#define BUSACK 6
#define DDR_BUSACK DDRD
//#define P_HALT PORTA
#define P_ADH PORTC
#define P_ADB PORTE
#define PIN_ADB PINE
-#define DDR_ADL DDRE
-#define DDR_ADH DDRE
+#define DDR_ADL DDRA
+#define DDR_ADH DDRC
#define DDR_ADB DDRE
#define ADB_WIDTH 3
//#define ADB_PORT PORTE
-
-#define ADp1_OFS 0
-#define ADp1_WIDTH 8
-#define ADp1_SHIFT 1
-#define ADp1_PORT GPIOA
-
-#define ADp2_OFS ADp1_WIDTH
-#define ADp2_WIDTH 8
-#define ADp2_SHIFT 0
-#define ADp2_PORT GPIOC
-
-#define ADp3_OFS (ADp2_OFS+ADp2_WIDTH)
-#define ADp3_WIDTH 3
-#define ADp3_SHIFT 10
-#define ADp3_PORT GPIOC
-
-#define ADunbuff1_WIDTH 1
-#define ADunbuff1_SHIFT 8
-#define ADunbuff1_PORT GPIOA
-
-#define ADunbuff2_WIDTH 2
-#define ADunbuff2_SHIFT 6
-#define ADunbuff2_PORT GPIOC
-
-#define ADunbuff3_WIDTH 3
-#define ADunbuff3_SHIFT 10
-#define ADunbuff3_PORT GPIOC
-
-#define DB_OFS 0
-#define DB_WIDTH 8
-#define DB_SHIFT 8
-#define DB_PORT GPIOB
-
-
+//#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
#define Z80_O_MREQ SBIT(P_MREQ, 4)
#define Z80_O_RD SBIT(P_RD, 3)
#define Z80_O_WR SBIT(P_WR, 2)
#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
//#define Z80_O_NMI SBIT(P_NMI, )
#define Z80_O_RST SBIT(P_RST, 5)
-#define Z80_I_BUSACK SBIT(P_BUSACK, 6)
+#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT SBIT(P_HALT, )
-void z80_busreq(level_t level)
-{
- Z80_O_BUSREQ = level;
-}
-
-void z80_reset(level_t level)
-{
- Z80_O_RST = level;
-}
-
-
-void z80_reset_pulse(void)
-{
- Z80_O_RST = 0;
- _delay_us(10);
- Z80_O_RST = 1;
-}
-
-#if 0
-int z80_stat_halt(void)
-{
- return Z80_I_HALT;
-}
-#endif
-
#define MASK(n) ((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))
-
typedef union {
uint32_t l;
uint16_t w[2];
uint8_t b[4];
} addr_t;
-
-/*--------------------------------------------------------------------------*/
+static zstate_t zstate;
+/*--------------------------------------------------------------------------*/
-/*
- * A0..A6, A8..A13 are buffered. No need to disable.
- * A7, A14..A18: set to input.
- */
-
-static void z80_setup_adrbus_tristate(void)
+
+static void z80_addrbus_set_tristate(void)
{
+ /* /MREQ, /RD, /WR: Input, no pullup */
+ DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
+ Z80_O_MREQ = 0;
+ Z80_O_RD = 0;
+ Z80_O_WR = 0;
+
P_ADL = 0;
DDR_ADL = 0;
P_ADH = 0;
DDR_ADH = 0;
- PIN_ADB = P_ADB & MASK(ADB_WIDTH) << ADB_SHIFT;
+ PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
}
-
-static void z80_setup_adrbus_active(void)
+
+static void z80_addrbus_set_active(void)
{
+ /* /MREQ, /RD, /WR: Output and high */
+ Z80_O_MREQ = 1;
+ Z80_O_RD = 1;
+ Z80_O_WR = 1;
+ DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);
+
DDR_ADL = 0xff;
DDR_ADH = 0xff;
DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
}
-
-static void z80_setup_dbus_in(void)
+static void z80_dbus_set_in(void)
{
DDR_DB = 0;
P_DB = 0;
}
-static void z80_setup_dbus_out(void)
+
+static void z80_dbus_set_out(void)
{
DDR_DB = 0xff;
}
-static
-void z80_setaddress(uint32_t addr)
-{
- addr_t x; x.l = addr;
- P_ADL = x.b[0];
- P_ADH = x.b[1];
- PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
+static void z80_reset_pulse(void)
+{
+ Z80_O_RST = 0;
+ _delay_us(10);
+ Z80_O_RST = 1;
}
+
void z80_setup_bus(void)
{
+ /* /ZRESET: Output and low */
Z80_O_RST = 0;
DDR_RST |= _BV(RST);
+ /* /BUSREQ: Output and high */
Z80_O_BUSREQ = 1;
DDR_BUSREQ |= _BV(BUSREQ);
-// Z80_O_NMI = 1;
-// DDR_NMI |= _BV(NMI);
-
- Z80_O_MREQ = 1;
- Z80_O_RD = 1;
- Z80_O_WR = 1;
- DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);
-
+ /* /BUSACK: Input, no pullup */
DDR_BUSACK &= ~_BV(BUSACK);
P_BUSACK &= ~_BV(BUSACK);
+ /* /IOCS1: Input, no pullup */
DDR_IOCS1 &= ~_BV(IOCS1);
P_IOCS1 &= ~_BV(IOCS1);
- //Z80_O_BUSREQ = 0;
- //while(Z80_I_BUSACK == 1);
+ z80_addrbus_set_tristate();
+ z80_dbus_set_in();
- z80_setup_adrbus_tristate();
- z80_setup_dbus_in();
+ zstate = RESET;
}
-void z80_request_bus(void)
+
+zstate_t z80_bus_state(void)
{
- Z80_O_BUSREQ = 0;
- while(Z80_I_BUSACK == 1);
- z80_setup_adrbus_active();
+ return zstate;
}
-void z80_release_bus(void)
+
+static void z80_busreq_hpulse(void)
{
- z80_setup_dbus_in();
- z80_setup_adrbus_tristate();
- Z80_O_BUSREQ = 1;
- while(Z80_I_BUSACK == 0);
+ z80_dbus_set_in();
+ z80_addrbus_set_tristate();
+
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ Z80_O_BUSREQ = 1;
+ Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
+ Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
+ }
+
+ if (zstate & ZST_ACQUIRED) {
+ while(Z80_I_BUSACK == 1)
+ ;
+ z80_addrbus_set_active();
+ }
+}
+
+
+/*
+
+ + | | | | |
+ + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
+ + | | | | |
+ + | 0 | 1 | 2 | 3 |
+Event + | | | | |
+----------------+---------------+---------------+---------------+---------------+
+ | | | | |
+Reset | 0 | 0 | 0 | 0 |
+ | | | | |
+ | | | | |
+Request | 1 | | 3 | |
+ | | | | |
+ | | | | |
+Release | | 0 | | 2 |
+ | | | | |
+ | | | | |
+Run | 2 | 3 | | |
+ | | | | |
+ | | | | |
+Restart | | | 2 | 3 |
+ | | | | |
+ | | | | |
+M_Cycle | | | | 3 |
+ | | | | |
+ | | | | |
+*/
+
+zstate_t z80_bus_cmd(bus_cmd_t cmd)
+{
+ switch (cmd) {
+
+ case Reset:
+ z80_dbus_set_in();
+ z80_addrbus_set_tristate();
+ Z80_O_RST = 0;
+ Z80_O_BUSREQ = 1;
+ zstate = RESET;
+ break;
+
+ case Request:
+ switch (zstate) {
+ case RESET:
+ Z80_O_BUSREQ = 0;
+ Z80_O_RST = 1;
+ while(Z80_I_BUSACK == 1)
+ ;
+ z80_addrbus_set_active();
+ zstate = RESET_AQRD;
+ break;
+
+ case RUNNING:
+ Z80_O_BUSREQ = 0;
+ while(Z80_I_BUSACK == 1)
+ ;
+ z80_addrbus_set_active();
+ zstate = RUNNING_AQRD;
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ case Release:
+ switch (zstate) {
+ case RESET_AQRD:
+ z80_dbus_set_in();
+ z80_addrbus_set_tristate();
+ Z80_O_RST = 0;
+ Z80_O_BUSREQ = 1;
+ zstate = RESET;
+ break;
+ case RUNNING_AQRD:
+ z80_dbus_set_in();
+ z80_addrbus_set_tristate();
+ Z80_O_BUSREQ = 1;
+ zstate = RUNNING;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case Run:
+ switch (zstate) {
+ case RESET:
+ Z80_O_RST = 1;
+ zstate = RUNNING;
+ break;
+
+ case RESET_AQRD:
+ z80_dbus_set_in();
+ z80_addrbus_set_tristate();
+ z80_reset_pulse();
+ z80_addrbus_set_active();
+ zstate = RUNNING_AQRD;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case Restart:
+ switch (zstate) {
+ case RUNNING:
+ case RUNNING_AQRD:
+ z80_reset_pulse();
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case M_Cycle:
+ switch (zstate) {
+ case RUNNING_AQRD:
+ z80_busreq_hpulse();
+ break;
+ default:
+ break;
+ }
+ }
+ return zstate;
+}
+
+
+/*--------------------------------------------------------------------------*/
+
+static
+//inline __attribute__ ((always_inline))
+void z80_setaddress(uint32_t addr)
+{
+ addr_t x; x.l = addr;
+
+ P_ADL = x.b[0];
+ P_ADH = x.b[1];
+ PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
}
void z80_write(uint32_t addr, uint8_t data)
{
z80_setaddress(addr);
Z80_O_MREQ = 0;
+ z80_dbus_set_out();
P_DB = data;
- z80_setup_dbus_out();
+ P_DB = data;
+ Z80_O_WR = 0;
Z80_O_WR = 0;
Z80_O_WR = 1;
Z80_O_MREQ = 1;
z80_setaddress(addr);
Z80_O_MREQ = 0;
- z80_setup_dbus_in();
+ z80_dbus_set_in();
+ Z80_O_RD = 0;
Z80_O_RD = 0;
Z80_O_RD = 0;
data = PIN_DB;
void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
{
- z80_setup_dbus_out();
+ z80_dbus_set_out();
Z80_O_MREQ = 0;
while(length--) {
z80_setaddress(addr++);
P_DB = data;
+ P_DB = data;
+ Z80_O_WR = 0;
Z80_O_WR = 0;
Z80_O_WR = 1;
}
Z80_O_MREQ = 1;
}
-void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length)
+void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
{
uint8_t data;
-
- z80_setup_dbus_out();
+
+ z80_dbus_set_out();
Z80_O_MREQ = 0;
while(length--) {
z80_setaddress(dest++);
data = *src++;
P_DB = data;
+ P_DB = data;
+ Z80_O_WR = 0;
Z80_O_WR = 0;
Z80_O_WR = 1;
}
017B' rx.out_idx: ds 1 ;
017C' rx.buf: ds rx.buf_len ;
018B' rx.buf_end equ $-1 ; last byte (start+len-1)
-
+
018C' tx.bs_mask: ds 1 ; (buf_len - 1)
018D' tx.in_idx: ds 1 ;
018E' tx.out_idx: ds 1 ;
idx_in,
mask;
} fifo_dsc[NUM_FIFOS];
-
-
-void z80_memfifo_init(const fifo_t f, uint32_t adr)
-{
-DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr);
- fifo_dsc[f].base = adr;
+void z80_memfifo_init(const fifo_t f, uint32_t addr)
+{
+ fifo_dsc[f].base = addr;
- z80_request_bus();
+ if (addr != 0) {
- fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
- fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
- fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);
+DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
- z80_release_bus();
+ z80_bus_cmd(Request);
+ fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
+ fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
+ fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
+ z80_bus_cmd(Release);
+ }
}
uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
uint8_t idx;
- z80_request_bus();
+ z80_bus_cmd(Request);
idx = z80_read(adr);
- z80_release_bus();
+ z80_bus_cmd(Release);
rc = idx == fifo_dsc[f].idx_out;
}
int z80_memfifo_is_full(const fifo_t f)
{
int rc = 1;
-
+
if (fifo_dsc[f].base != 0) {
- z80_request_bus();
+ z80_bus_cmd(Request);
rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
- z80_release_bus();
+ z80_bus_cmd(Release);
}
return rc;
}
-uint8_t z80_memfifo_getc(const fifo_t f)
+
+uint8_t z80_memfifo_getc_wait(const fifo_t f)
{
uint8_t rc, idx;
-
+
while (z80_memfifo_is_empty(f))
;
- z80_request_bus();
+ z80_bus_cmd(Request);
idx = fifo_dsc[f].idx_out;
rc = z80_read(fifo_dsc[f].base+idx);
fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
- z80_release_bus();
-
+ z80_bus_cmd(Release);
+
+ return rc;
+}
+
+int z80_memfifo_getc(const fifo_t f)
+{
+ int rc = -1;
+
+ if (fifo_dsc[f].base != 0) {
+ uint8_t idx = fifo_dsc[f].idx_out;
+ z80_bus_cmd(Request);
+ if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
+ rc = z80_read(fifo_dsc[f].base+idx);
+ fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
+ z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
+ }
+ z80_bus_cmd(Release);
+ }
+
return rc;
}
void z80_memfifo_putc(fifo_t f, uint8_t val)
{
int idx;
-
+
while (z80_memfifo_is_full(f))
;
- z80_request_bus();
+ z80_bus_cmd(Request);
idx = fifo_dsc[f].idx_in;
z80_write(fifo_dsc[f].base+idx, val);
fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
- z80_release_bus();
-}
-
-/*--------------------------------------------------------------------------*/
-
-static struct {
- uint32_t base;
- //uint8_t idx_out, idx_in;
- uint16_t count;
- uint8_t buf[256];
- } msg_fifo;
-
-/*--------------------------------------------------------------------------*/
-
-#if 0
-
-static void tim1_setup(void)
-{
- RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
- RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
-
- TIM1_CR1 = 0;
-
- TIM1_SMCR = 0
- /* | TIM_SMCR_ETP */
- /* | TIM_SMCR_ETF_CK_INT_N_2 */
- | TIM_SMCR_TS_ETRF
- | TIM_SMCR_SMS_OFF
- ;
-
- TIM1_DIER = TIM_DIER_TDE;
-
-
- TIM1_CCMR1 = 0
- | TIM_CCMR1_OC1M_FORCE_LOW
- | TIM_CCMR1_CC1S_OUT;
-
- TIM1_SMCR |= TIM_SMCR_SMS_TM;
-}
-
-#endif
-
-/*--------------------------------------------------------------------------*/
-
-void z80_setup_msg_fifo(void)
-{
-// gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
-// GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);
-
-//...
-
-// msg_fifo.count = NELEMS(msg_fifo.buf);
- msg_fifo.count = 0;
- msg_fifo.base = 0;
-
-}
-
-
-void z80_init_msg_fifo(uint32_t addr)
-{
-
-DBG_P(1, "z80_init_msg_fifo: %lx\n", addr);
-
- z80_request_bus();
- z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN));
- z80_release_bus();
- msg_fifo.base = addr;
-}
-
-
-int z80_msg_fifo_getc(void)
-{
- int c = -1;
-
- if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) {
- c = msg_fifo.buf[msg_fifo.count];
- if (++msg_fifo.count == NELEMS(msg_fifo.buf))
- msg_fifo.count = 0;
-
- if (msg_fifo.base != 0) {
- z80_request_bus();
- z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count);
- z80_release_bus();
- }
- }
-
- return c;
+ z80_bus_cmd(Release);
}
projects / z180-stamp.git / blobdiff