cli.c bugfix: Comment only lines are not an error.

[z180-stamp.git] / z180 / z180reg.inc

diff --git a/z180/z180reg.inc b/z180/z180reg.inc
index 271a4468a1593074f44bb7790c0ec9cbadc5cf28..a1a90c27d1987035ed4484b9b5ba802c15ed5c6d 100644 (file)
--- a/z180/z180reg.inc
+++ b/z180/z180reg.inc
@@ -24,7 +24,7 @@ cntla1        equ     IOBASE+01h      ;ASCI Control Register A Channel 1
        b2m MPBR, 3             ;Multiprocessor Bit Receive (Read)\r
        b2m EFR, 3              ;Error Flag Reset (Write)\r
        b2m MOD2, 2             ;Data Format Mode 1 = 8-Bit data\r
-       b2m NOD1, 1             ;1 = Parity enabled\r
+       b2m MOD1, 1             ;1 = Parity enabled\r
        b2m MOD0, 0             ;1 = 2 stop bits\r
 \r
 cntlb0 equ     IOBASE+02h      ;ASCI Control Register B Channel 0\r
@@ -47,7 +47,7 @@ stat1 equ     IOBASE+05h      ;ASCI Status Channel 1
        b2m FE,4                ;Framing Error\r
        b2m RIE,3               ;Receive Interrupt Enable\r
        b2m DCD0,2              ;Data Carrier Detect (Ch 0)\r
-       b2m CTS1E,2             ;Clear To Send (Ch 1)\r
+       b2m CTS1E,2             ;Clear To Send Enable (Ch 1)\r
        b2m TDRE,1              ;Transmit Data Register Empty\r
        b2m TIE,0               ;Transmit Interrupt Enable\r
 \r
@@ -130,8 +130,8 @@ bcr1h       equ     IOBASE+2Fh      ;
 dstat  equ     IOBASE+30h      ;DMA Status Register\r
        b2m DE1,7               ;DMA enable ch 1,0\r
        b2m DE0,6               ;\r
-       b2m DWE1,5              ;DMA Enable Bit Write Enable 1,0\r
-       b2m DWE0,4              ;\r
+       b2m NDWE1,5             ;DMA Enable Bit Write Enable 1,0\r
+       b2m NDWE0,4             ;\r
        b2m DIE1,3              ;DMA Interrupt Enable 1,0\r
        b2m DIE0,2              ;\r
        b2m DME,0               ;DMA Master enable\r
@@ -195,4 +195,3 @@ IV$ASCI0 equ        14              ;ASCI channel 0
 IV$ASCI1 equ   16              ;ASCI channel 1 (lowest priority)\r
 \r
        .list\r
-\r