switch fifos conin,conout

[z180-stamp.git] / z180 / config.inc

diff --git a/z180/config.inc b/z180/config.inc
index 390d3bc9cf1b64595a83e5ef16b112129c3c2e33..2a8a842d0c4067f00f38425fab6c66601b3b9490 100644 (file)
--- a/z180/config.inc
+++ b/z180/config.inc
@@ -1,18 +1,43 @@
+\r
+FALSE  equ     0\r
+TRUE   equ     NOT FALSE\r
+\r
+\r
+DEBUG  equ     true\r
+\r
+banked equ     true\r
+\r
 ;-----------------------------------------------------\r
 ; CPU and BANKING types\r
 \r
 \r
-CPU_Z180       equ     1               ; 0 = Z80, else Z180\r
-ROMSYS         equ     0\r
+CPU_Z180       equ     TRUE\r
+CPU_Z80                equ     FALSE\r
+\r
+ROMSYS         equ     FALSE\r
 \r
 AVRCLK         equ     18432           ;[KHz]\r
 \r
-       if CPU_Z180\r
+    if CPU_Z180\r
 \r
 ;-----------------------------------------------------\r
 FOSC           equ     AVRCLK/2        ;Oscillator frequency [KHz]\r
 PHI            equ     FOSC*2          ;CPU frequency (clock doubler enabled)\r
 \r
+;----------------------------------------------------------------------\r
+; Baudrate Generator for x16 clock mode:\r
+; TC = (f PHI / (32 * baudrate)) - 2\r
+;\r
+;     PHI [MHz]: 9.216 18.432\r
+;     baudrate     TC     TC\r
+;     ----------------------\r
+;      115200      -      3\r
+;      57600       3      8\r
+;      38400       -     13\r
+;      19200      13     28\r
+;       9600      28     58\r
+\r
+\r
 ;-----------------------------------------------------\r
 ; Programmable Reload Timer (PRT)\r
 \r
@@ -26,8 +51,21 @@ PRT_TC10MS   equ     PHI / (PRT_PRE/10)
 ;-----------------------------------------------------\r
 ; MMU\r
 \r
-SYS$CBAR       equ     0C8h\r
-USR$CBAR       equ     0F0h\r
+COMMON_SIZE    equ     16*1024         ;Common Area size in bytes\r
+                                       ;must be multiple of 4K\r
+\r
+if (COMMON_SIZE mod 1000h)\r
+       .printx COMMON_SIZE not multiple of 4K!\r
+       end     ;stop assembly\r
+endif\r
+\r
+CSK    equ     COMMON_SIZE/1000h       ;\r
+CA     equ     10h - CSK               ;common area start\r
+BA     equ     0                       ;banked area start\r
+\r
+SYS$CBR                equ     0\r
+SYS$CBAR       equ     CA*16 + CA      ;CBAR in system mode\r
+USR$CBAR       equ     CA*16 + BA      ;CBAR in user mode (CP/M)\r
 \r
 \r
 BANKS          equ     18              ;max nr. of banks\r
@@ -36,8 +74,10 @@ BANKS                equ     18              ;max nr. of banks
 \r
 CREFSH         equ     0               ;Refresh rate register (disable refresh)\r
 CWAITIO                equ     3 shl IWI0      ;Max I/O Wait States, 0 Memory Wait States\r
+PHI_X2         equ     0               ;set to M_X2CM to enable the clock doubler\r
 \r
-       else    ; Z80\r
+    endif              ;CPU_Z180\r
+    if CPU_Z80\r
 \r
 PHI            equ     AVRCLK/5        ;CPU frequency [KHz]\r
 BAUDCLCK       equ     AVRCLK/10       ;Baudrate clock [KHz]\r
@@ -71,39 +111,47 @@ CTC3       EQU     0f7h
 ;    600       3072     16     192\r
 ;    300       6144     64      92\r
 \r
-       endif   ; CPU_Z180\r
+    endif      ; CPU_Z80\r
 \r
-       if      ROMSYS\r
+    if ROMSYS\r
 c$rom          equ     0a5h\r
 ROM_EN         equ     0C0h\r
 ROM_DIS                equ     ROMEN+1\r
-       if CPU_Z180\r
+     if CPU_Z180\r
 CWAITROM       equ     2 shl MWI0\r
-       endif\r
-       endif\r
+     endif\r
+    endif\r
 \r
 \r
-DRSTNUM        equ     30h             ;DDTZ Restart vector (breakpoints)\r
+DDTZRSTVEC     equ     030h            ;DDTZ Restart vector (breakpoints)\r
 \r
+INIDONE                equ     03Fh            ;CP/M skip hw init, if this address\r
+INIDONEVAL     equ     080h            ;    is set to this value.\r
 \r
-mrx.fifo_len   equ     256\r
-mtx.fifo_len   equ     256\r
+mtx.fifo_len   equ     32              ;Message transfer fifos\r
+mtx.fifo_id    equ     0               ;    This *must* have #0\r
+mrx.fifo_len   equ     32\r
+mrx.fifo_id    equ     1\r
 \r
-ci.fifo_len    equ     128\r
-co.fifo_len    equ     256\r
+ci.fifo_len    equ     32              ;AVRCON Character I/O via AVR\r
+ci.fifo_id     equ     2\r
+co.fifo_len    equ     32\r
+co.fifo_id     equ     3\r
 \r
-s1.rx_len      equ     256             ;Serial 1 (ASCI1) buffers\r
-s1.tx_len      equ     256             ;\r
+s1.rx_len      equ     128             ;Serial 1 (ASCI1) buffers\r
+s1.rx_id       equ     4               ;\r
+s1.tx_len      equ     128             ;\r
+s1.tx_id       equ     5               ;\r
 \r
 AVRINT5                equ     4Fh\r
 AVRINT6                equ     5Fh\r
 ;PMSG          equ     80h\r
 \r
 ;-----------------------------------------------------\r
-; Definition of (locical) top 2 memory pages\r
+; Definition of (logical) top 2 memory pages\r
 \r
 sysram_start   equ     0FE00h\r
-stacksize      equ     80\r
+bs$stack$size  equ     80\r
 \r
 isvsw_loc      equ     0FEE0h\r
 \r
@@ -114,24 +162,26 @@ iv2tab            equ     ivtab + 2*9
 \r
 ;-----------------------------------------------------\r
 \r
-\r
+o.id           equ     -4\r
 o.mask         equ     -3\r
 o.in_idx       equ     -2\r
 o.out_idx      equ     -1\r
 \r
        .lall\r
 \r
-mkbuf  macro   name,size\r
-  if ((size & (size-1)) ne 0) or (size gt 256)\r
+mkbuf  macro   id,name,size\r
+  if ((size AND (size-1)) NE 0) OR (size GT 256)\r
     .printx Error: buffer ^size must be power of 2 and in range 0..256!\r
     name&.mask equ ;wrong size error\r
   else\r
+    db id\r
     ds 3\r
     name:: ds size\r
     name&.mask equ low (size-1)\r
     if size ne 0\r
       name&.end equ $-1\r
       name&.len equ size\r
+      name&.id equ id\r
     endif\r
   endif\r
 endm\r
@@ -149,3 +199,9 @@ inidate     macro
        ds      ??ps.len\r
        endm\r
 \r
+;-----------------------------------------------------\r
+\r
+b0call macro   address\r
+       call    _b0call\r
+       dw      address\r
+       endm\r