+/*
+ * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
/**
*
* Pin assignments
*
- * | Z180-Sig | AVR-Port | Dir | Special Function |
- * +------------+---------------+-------+-----------------------+
- * | A0 | PA 0 | O | |
- * | A1 | PA 1 | O | |
- * | A2 | PA 2 | O | |
- * | A3 | PA 3 | O | |
- * | A4 | PA 4 | O | |
- * | A5 | PA 5 | O | |
- * | A6 | PA 6 | O | |
- * | A7 | PA 7 | O | |
- * | A8 | PC 0 | O | |
- * | A9 | PC 1 | O | |
- * | A10 | PC 2 | O | |
- * | A11 | PC 3 | O | |
- * | A12 | PC 4 | O | |
- * | A13 | PC 5 | O | |
- * | A14 | PC 6 | O | |
- * | A15 | PC 7 | O | |
- * | A16 | PE 2 | O | |
- * | A17 | PE 3 | O | |
- * | A18 | PE 4 | O | |
- * | D0 | PF 0 | I/O | |
- * | D1 | PF 1 | I/O | |
- * | D2 | PF 2 | I/O | |
- * | D3 | PF 3 | I/O | |
- * | D4 | PF 4 | I/O | |
- * | D5 | PF 5 | I/O | |
- * | D6 | PF 6 | I/O | |
- * | D7 | PF 7 | I/O | |
- * | RD | PD 3 | O | |
- * | WR | PD 2 | O | |
- * | MREQ | PD 4 | O | |
- * | RST | PD 5 | O | |
- * | BUSREQ | PD 7 | O | |
- * | BUSACK | PD 6 | I | |
- * | IOCS1 | PE 5 | I | |
- * |* HALT | P | | |
- * |* NMI | P | | |
- * | | P | | |
- * | | P | | af1 USART1_TX |
- * | | P | | af1 USART1_RX |
- * | | P |JTDI | remap SPI1_NSS' |
- * | | P |JTDO | remap SPI1_SCK' |
- * | | P |JTRST | remap SPI1_MISO' |
- * | | P | | remap SPI1_MOSI' |
- * | | P | | af1 OSC32 |
- * | | P | | af1 OSC32 |
-
+ * | Z180-Sig | AVR-Port | Dir |
+ * +------------+---------------+-------+
+ * | A0 | PA 0 | O |
+ * | A1 | PA 1 | O |
+ * | A2 | PA 2 | O |
+ * | A3 | PA 3 | O |
+ * | A4 | PA 4 | O |
+ * | A5 | PA 5 | O |
+ * | A6 | PA 6 | O |
+ * | A7 | PA 7 | O |
+ * | A8 | PC 0 | O |
+ * | A9 | PC 1 | O |
+ * | A10 | PC 2 | O |
+ * | A11 | PC 3 | O |
+ * | A12 | PC 4 | O |
+ * | A13 | PC 5 | O |
+ * | A14 | PC 6 | O |
+ * | A15 | PC 7 | O |
+ * | A16 | PE 2 | O |
+ * | A17 | PE 3 | O |
+ * | A18 | PE 4 | O |
+ * | D0 | PF 0 | I/O |
+ * | D1 | PF 1 | I/O |
+ * | D2 | PF 2 | I/O |
+ * | D3 | PF 3 | I/O |
+ * | D4 | PF 4 | I/O |
+ * | D5 | PF 5 | I/O |
+ * | D6 | PF 6 | I/O |
+ * | D7 | PF 7 | I/O |
+ * | RD | PD 3 | O |
+ * | WR | PD 2 | O |
+ * | MREQ | PD 4 | O |
+ * | RST | PD 5 | O |
+ * | BUSREQ | PD 7 | O |
+ * | BUSACK | PD 6 | I |
+ * |
+ * | Optional
+ * +------------------------------------+
+ * | STEP | PG 0 | O |
+ * | RUN | PG 1 | O |
+ * | WAIT | PG 2 | I |
*/
-#include <avr/io.h>
-#include <util/delay.h>
+
+#include "z80-if.h"
#include <util/atomic.h>
-#include <stdio.h>
#include "debug.h"
-#include "z80-if.h"
-
-
-/* Number of array elements */
-#define NELEMS(x) (sizeof x/sizeof *x)
-
+#include "config.h"
+#include "env.h"
-#define CONCAT(x,y) x ## y
-#define EVALUATOR(x,y) CONCAT(x,y)
-#define GPIO_(X) CONCAT(GPIO, X)
-
-struct bits {
- uint8_t b0:1;
- uint8_t b1:1;
- uint8_t b2:1;
- uint8_t b3:1;
- uint8_t b4:1;
- uint8_t b5:1;
- uint8_t b6:1;
- uint8_t b7:1;
-} __attribute__((__packed__));
-
-#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
-
-
-#define P_ZCLK PORTB
-#define ZCLK 7
-#define DDR_ZCLK DDRB
+//#define P_ZCLK PORTB
+//#define ZCLK 5
+//#define DDR_ZCLK DDRB
#define P_MREQ PORTD
#define MREQ 4
#define DDR_MREQ DDRD
#define PIN_BUSACK PIND
#define BUSACK 6
#define DDR_BUSACK DDRD
-//#define P_HALT PORTA
-//#define HALT 12
-#define P_IOCS1 PORTE
-#define IOCS1 5
-#define DDR_IOCS1 DDRE
-//#define P_NMI PORTB
-//#define NMI 7
#define P_RST PORTD
#define DDR_RST DDRD
#define RST 5
//#define ADB_PORT PORTE
-#define Z80_O_ZCLK SBIT(P_ZCLK, 7)
+//#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
#define Z80_O_MREQ SBIT(P_MREQ, 4)
#define Z80_O_RD SBIT(P_RD, 3)
#define Z80_O_WR SBIT(P_WR, 2)
#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT SBIT(P_HALT, )
+/* Optional */
+#define P_RUN PORTG
+#define RUN 1
+#define DDR_RUN DDRG
+#define P_STEP PORTG
+#define STEP 0
+#define DDR_STEP DDRG
+#define P_WAIT PORTG
+#define WAIT 2
+#define DDR_WAIT DDRG
+/* All three signals are on the same Port (PortG) */
+#define PORT_SS PORTG
+#define DDR_SS DDRG
+#define PIN_SS PING
+#define Z80_O_RUN SBIT(PORT_SS, RUN)
+#define Z80_O_STEP SBIT(PORT_SS, STEP)
+#define Z80_I_WAIT SBIT(PORT_SS, WAIT)
-#define MASK(n) ((1<<(n))-1)
-#define SMASK(w,s) (MASK(w) << (s))
-#define LOWSPEED 50000
+#define BUS_TO 20
-typedef union {
- uint32_t l;
- uint16_t w[2];
- uint8_t b[4];
-} addr_t;
+#define MASK(n) ((1<<(n))-1)
+#define SMASK(w,s) (MASK(w) << (s))
static zstate_t zstate;
+static volatile uint8_t timer; /* used for bus timeout */
-/*--------------------------------------------------------------------------*/
-
-static
-uint8_t is_lowspeed()
-{
- return (TCCR1B & 7) < 2 &&
- OCR1A > (F_CPU / 2 / LOWSPEED);
-}
-
-static
-void z80_setup_clock(void)
-{
- /* ZCLK: Output and low */
- DDR_ZCLK |= _BV(ZCLK);
- Z80_O_ZCLK = 0;
-
- DDRB |= _BV(6); /* Debug */
- PORTB |= _BV(6); /* Debug */
-
- PRR0 &= ~_BV(PRTIM1);
-
- /* Timer1: CTC: Toggle OC1C on compare match */
- OCR1A = 0;
- OCR1C = 0;
- TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10);
- TCCR1B = (0b01 << WGM12) | (0b001 << CS10);
-}
-
+/*---------------------------------------------------------*/
+/* 10Hz timer interrupt generated by OC4A */
+/*---------------------------------------------------------*/
-int z80_clock_set(unsigned long freq)
+ISR(TIMER5_COMPA_vect)
{
- unsigned long ocrval = F_CPU / freq / 2;
- uint8_t prescale = 0;
-
- while (ocrval > (1L<<16)) {
- prescale++;
- if (prescale < 3)
- ocrval = ocrval / 8;
- else
- ocrval = ocrval / 4;
- }
-
- if ((ocrval == 0) || (prescale > 4))
- return -1;
-
- ocrval -= 1;
-
- PINB |= _BV(6); /* Debug */
-
- /* Stop Timer */
- TCCR1B = (0b01 << WGM12) | (0b000 << CS10);
- TCNT1 = 0;
-
- OCR1A = ocrval;
- OCR1CL = ocrval;
- TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10);
- TCCR1B = (0b01 << WGM12) | ((prescale+1) << CS10);
-
- if (ocrval == 0)
- ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
- TCNT1 = 0xFFFF;
- }
-
- PINB |= _BV(6); /* Debug */
-
- return 0;
-}
-uint32_t z80_clock_get(void)
-{
- uint32_t count = (OCR1A + 1L) * 2;
- uint8_t pre = (TCCR1B & 7) - 1;
-
- while (pre) {
- if (pre > 2)
- count *= 4;
- else
- count *= 8;
- pre--;
- }
+ uint8_t i = timer;
- return F_CPU/count;
+ if (i)
+ timer = i - 1;
}
+/*--------------------------------------------------------------------------*/
-static void z80_addrbus_set_tristate(void)
+static void z80_addrbus_set_in(void)
{
/* /MREQ, /RD, /WR: Input, no pullup */
DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
DDR_ADL = 0;
P_ADH = 0;
DDR_ADH = 0;
- PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
+ PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT);
DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
}
-static void z80_addrbus_set_active(void)
+static void z80_addrbus_set_out(void)
{
/* /MREQ, /RD, /WR: Output and high */
Z80_O_MREQ = 1;
void z80_setup_bus(void)
{
- z80_setup_clock();
+ ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
- /* /ZRESET: Output and low */
- Z80_O_RST = 0;
- DDR_RST |= _BV(RST);
+ /* /ZRESET: Output and low */
+ Z80_O_RST = 0;
+ DDR_RST |= _BV(RST);
- /* /BUSREQ: Output and high */
- Z80_O_BUSREQ = 1;
- DDR_BUSREQ |= _BV(BUSREQ);
+ /* /BUSREQ: Output and high */
+ Z80_O_BUSREQ = 1;
+ DDR_BUSREQ |= _BV(BUSREQ);
- /* /BUSACK: Input, no pullup */
- DDR_BUSACK &= ~_BV(BUSACK);
- P_BUSACK &= ~_BV(BUSACK);
+ /* /BUSACK: Input, no pullup */
+ DDR_BUSACK &= ~_BV(BUSACK);
+ P_BUSACK &= ~_BV(BUSACK);
- /* /IOCS1: Input, no pullup */
- DDR_IOCS1 &= ~_BV(IOCS1);
- P_IOCS1 &= ~_BV(IOCS1);
+ z80_addrbus_set_in();
+ z80_dbus_set_in();
- z80_addrbus_set_tristate();
- z80_dbus_set_in();
+ if (getenv_yesno(PSTR(ENV_SINGLESTEP))) {
+ /* /RUN & /STEP: output, /WAIT: input */
+
+ PORT_SS = (PORT_SS & ~_BV(RUN)) | _BV(STEP);
+ DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
+ }
+
+ zstate = RESET;
+ }
+
+ /* Timer 5 */
+ PRR1 &= ~_BV(PRTIM5);
+ OCR5A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
+ TCCR5B = (0b01<<WGM52)|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */
+ TIMSK5 = _BV(OCIE5A); /* Enable oca interrupt */
- zstate = RESET;
}
static void z80_busreq_hpulse(void)
{
z80_dbus_set_in();
- z80_addrbus_set_tristate();
+ z80_addrbus_set_in();
- ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
+#if 0
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
Z80_O_BUSREQ = 1;
Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
}
+#endif
+
+#if 1
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ Z80_O_BUSREQ = 1;
+
+ do {
+ if (Z80_I_BUSACK == 1) {
+ Z80_O_BUSREQ = 0;
+ break;
+ }
+ } while (1);
+ }
+#endif
if (zstate & ZST_ACQUIRED) {
- while(Z80_I_BUSACK == 1)
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 1 && timer)
;
- z80_addrbus_set_active();
+ if (Z80_I_BUSACK == 0)
+ z80_addrbus_set_out();
}
}
/*
- + | | | | |
+ + | | | | |
+ State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
- + | | | | |
- + | 0 | 1 | 2 | 3 |
-Event + | | | | |
+ + | | | | |
+ + | 0 | 1 | 2 | 3 |
+Event + | | | | |
----------------+---------------+---------------+---------------+---------------+
- | | | | |
-Reset | 0 | 0 | 0 | 0 |
- | | | | |
- | | | | |
-Request | 1 | | 3 | |
- | | | | |
- | | | | |
-Release | | 0 | | 2 |
- | | | | |
- | | | | |
-Run | 2 | 3 | | |
- | | | | |
- | | | | |
-Restart | | | 2 | 3 |
- | | | | |
- | | | | |
-M_Cycle | | | | 3 |
- | | | | |
- | | | | |
+ | | | | |
+Reset | 0 | 0 | 0 | 0 |
+ | | | | |
+ | | | | |
+Request | 1 | | 3 | |
+ | | | | |
+ | | | | |
+Release | | 0 | | 2 |
+ | | | | |
+ | | | | |
+Run | 2 | 3 | | |
+ | | | | |
+ | | | | |
+Restart | | | 2 | 3 |
+ | | | | |
+ | | | | |
+M_Cycle | | | | 3 |
+ | | | | |
+ | | | | |
*/
zstate_t z80_bus_cmd(bus_cmd_t cmd)
case Reset:
z80_dbus_set_in();
- z80_addrbus_set_tristate();
+ z80_addrbus_set_in();
Z80_O_RST = 0;
Z80_O_BUSREQ = 1;
zstate = RESET;
case RESET:
Z80_O_BUSREQ = 0;
Z80_O_RST = 1;
- while(Z80_I_BUSACK == 1)
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 1 && timer)
;
- z80_addrbus_set_active();
- zstate = RESET_AQRD;
+ if (Z80_I_BUSACK == 0) {
+ z80_addrbus_set_out();
+ zstate = RESET_AQRD;
+ } else {
+ Z80_O_RST = 0;
+ Z80_O_BUSREQ = 1;
+ }
break;
case RUNNING:
Z80_O_BUSREQ = 0;
- while(Z80_I_BUSACK == 1)
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 1 && timer)
;
- z80_addrbus_set_active();
- zstate = RUNNING_AQRD;
+ if (Z80_I_BUSACK == 0) {
+ z80_addrbus_set_out();
+ zstate = RUNNING_AQRD;
+ } else {
+ Z80_O_BUSREQ = 1;
+ }
break;
default:
switch (zstate) {
case RESET_AQRD:
z80_dbus_set_in();
- z80_addrbus_set_tristate();
+ z80_addrbus_set_in();
Z80_O_RST = 0;
Z80_O_BUSREQ = 1;
zstate = RESET;
break;
case RUNNING_AQRD:
z80_dbus_set_in();
- z80_addrbus_set_tristate();
+ z80_addrbus_set_in();
Z80_O_BUSREQ = 1;
zstate = RUNNING;
break;
case RESET_AQRD:
z80_dbus_set_in();
- z80_addrbus_set_tristate();
+ z80_addrbus_set_in();
z80_reset_pulse();
- z80_addrbus_set_active();
+ z80_addrbus_set_out();
zstate = RUNNING_AQRD;
break;
default:
case M_Cycle:
switch (zstate) {
case RUNNING_AQRD:
- z80_busreq_hpulse();
+ z80_busreq_hpulse(); /* TODO: */
break;
default:
break;
//inline __attribute__ ((always_inline))
void z80_setaddress(uint32_t addr)
{
- addr_t x; x.l = addr;
-
- P_ADL = x.b[0];
- P_ADH = x.b[1];
- PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
+ P_ADL = addr;
+ P_ADH = (addr & 0xff00) >> 8;
+ PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
}
void z80_write(uint32_t addr, uint8_t data)
{
z80_dbus_set_out();
Z80_O_MREQ = 0;
+ P_DB = data;
while(length--) {
z80_setaddress(addr++);
+ Z80_O_WR = 0;
+ Z80_O_WR = 0;
+ Z80_O_WR = 1;
+ }
+ Z80_O_MREQ = 1;
+}
+
+void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
+{
+ uint8_t data;
+
+ z80_dbus_set_out();
+ Z80_O_MREQ = 0;
+ while(length--) {
+ z80_setaddress(dest++);
+ data = *src++;
P_DB = data;
P_DB = data;
Z80_O_WR = 0;
Z80_O_MREQ = 1;
}
-void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
+void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
{
uint8_t data;
Z80_O_MREQ = 1;
}
+void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
+{
+ uint8_t data;
+
+ Z80_O_MREQ = 0;
+ z80_dbus_set_in();
+ while(length--) {
+ z80_setaddress(src++);
+ Z80_O_RD = 0;
+ Z80_O_RD = 0;
+ Z80_O_RD = 0;
+ data = PIN_DB;
+ Z80_O_RD = 1;
+ *dest++ = data;
+ }
+ Z80_O_MREQ = 1;
+}
+
+
/*
0179' rx.bs_mask: ds 1 ; (buf_len - 1)
017A' rx.in_idx: ds 1 ;
} fifo_dsc[NUM_FIFOS];
-void z80_memfifo_init(const fifo_t f, uint32_t adr)
+void z80_memfifo_init(const fifo_t f, uint32_t addr)
{
+ fifo_dsc[f].base = addr;
-DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr);
+DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
- fifo_dsc[f].base = adr;
-
- z80_bus_cmd(Request);
-
- fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
- fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
- fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);
-
- z80_bus_cmd(Release);
+ if (addr != 0) {
+ z80_bus_cmd(Request);
+ fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
+ fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
+ fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
+ z80_bus_cmd(Release);
+ }
}
int z80_memfifo_is_full(const fifo_t f)
{
- int rc = 1;
+ int rc = 0;
if (fifo_dsc[f].base != 0) {
z80_bus_cmd(Request);
return rc;
}
-uint8_t z80_memfifo_getc(const fifo_t f)
+
+uint8_t z80_memfifo_getc_wait(const fifo_t f)
{
uint8_t rc, idx;
return rc;
}
+int z80_memfifo_getc(const fifo_t f)
+{
+ int rc = -1;
+
+ if (fifo_dsc[f].base != 0) {
+ uint8_t idx = fifo_dsc[f].idx_out;
+ z80_bus_cmd(Request);
+ if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
+ rc = z80_read(fifo_dsc[f].base+idx);
+ fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
+ z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
+ }
+ z80_bus_cmd(Release);
+ }
+
+ return rc;
+}
+
void z80_memfifo_putc(fifo_t f, uint8_t val)
{
z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
z80_bus_cmd(Release);
}
-
-/*--------------------------------------------------------------------------*/
-/*
- TODO: Rewrite msg_fifo routines for AVR
-*/
-
-static struct {
- uint32_t base;
- //uint8_t idx_out, idx_in;
- uint16_t count;
- uint8_t buf[256];
- } msg_fifo;
-
-/*--------------------------------------------------------------------------*/
-
-#if 0
-
-static void tim1_setup(void)
-{
- RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
- RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
-
- TIM1_CR1 = 0;
-
- TIM1_SMCR = 0
- /* | TIM_SMCR_ETP */
- /* | TIM_SMCR_ETF_CK_INT_N_2 */
- | TIM_SMCR_TS_ETRF
- | TIM_SMCR_SMS_OFF
- ;
-
- TIM1_DIER = TIM_DIER_TDE;
-
-
- TIM1_CCMR1 = 0
- | TIM_CCMR1_OC1M_FORCE_LOW
- | TIM_CCMR1_CC1S_OUT;
-
- TIM1_SMCR |= TIM_SMCR_SMS_TM;
-}
-
-#endif
-
-/*--------------------------------------------------------------------------*/
-
-void z80_setup_msg_fifo(void)
-{
-
-
-// gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
-// GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);
-
-//...
-
-// msg_fifo.count = NELEMS(msg_fifo.buf);
- msg_fifo.count = 0;
- msg_fifo.base = 0;
-
-}
-
-
-void z80_init_msg_fifo(uint32_t addr)
-{
-
-DBG_P(1, "z80_init_msg_fifo: %lx\n", addr);
-
- z80_bus_cmd(Request);
- z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN));
- z80_bus_cmd(Release);
- msg_fifo.base = addr;
-}
-
-
-int z80_msg_fifo_getc(void)
-{
- int c = -1;
-
-#if 0
- if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) {
- c = msg_fifo.buf[msg_fifo.count];
- if (++msg_fifo.count == NELEMS(msg_fifo.buf))
- msg_fifo.count = 0;
-
- if (msg_fifo.base != 0) {
- z80_bus_cmd(Request);
- z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count);
- z80_bus_cmd(Release);
- }
- }
-#endif
-
- return c;
-}
projects / z180-stamp.git / blobdiff