b2m TDRE,1 ;Transmit Data Register Empty\r
b2m TIE,0 ;Transmit Interrupt Enable\r
\r
-tdr0 equ IOBASE+06h ;ASCI Transmit Data \r
-tdr1 equ IOBASE+07h ;ASCI Transmit Data \r
-rdr0 equ IOBASE+08h ;ASCI Receive Data \r
-rdr1 equ IOBASE+09h ;ASCI Receive Data \r
+tdr0 equ IOBASE+06h ;ASCI Transmit Data\r
+tdr1 equ IOBASE+07h ;ASCI Transmit Data\r
+rdr0 equ IOBASE+08h ;ASCI Receive Data\r
+rdr1 equ IOBASE+09h ;ASCI Receive Data\r
\r
cntr equ IOBASE+0Ah ;CSI/O Control Register\r
trdr equ IOBASE+0Bh ;CSI/O Transmit/Receive Data Register\r
b2m LNC,6 ;Low Noise Crystal\r
\r
ccr equ IOBASE+1Fh ;CPU Control Register\r
+ b2m NCD 7 ;No Clock Divide\r
\r
sar0l equ IOBASE+20h ;DMA Src Adr Register Channel 0\r
sar0h equ IOBASE+21h ;\r