+/*
+ * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/**
+ *
+ * Pin assignments
+ *
+ * | Z180-Sig | STM32-Port |Buffer | Dir | Special Function |
+ * +------------+---------------+-------+-------+-----------------------+
+ * | A0 | A 1 | P | O | |
+ * | A1 | A 2 | P | O | |
+ * | A2 | A 3 | P | O | |
+ * | A3 | A 4 | P | O | |
+ * | A4 | A 5 | P | O | |
+ * | A5 | A 6 | P | O | |
+ * | A6 | A 7 | P | O | |
+ * | A7 | A 8 | | O | |
+ * | A8 | C 0 | P | O | |
+ * | A9 | C 1 | P | O | |
+ * | A10 | C 2 | P | O | |
+ * | A11 | C 3 | P | O | |
+ * | A12 | C 4 | P | O | |
+ * | A13 | C 5 | P | O | |
+ * | A14 | C 6 | | O | |
+ * | A15 | C 7 | | O | |
+ * | A16 | C 10 | | O | |
+ * | A17 | C 11 | | O | |
+ * | A18 | C 12 | | O | |
+ * | D0 | B 8 | | I/O | |
+ * | D1 | B 9 | | I/O | |
+ * | D2 | B 10 | | I/O | |
+ * | D3 | B 11 | | I/O | |
+ * | D4 | B 12 | | I/O | |
+ * | D5 | B 13 | | I/O | |
+ * | D6 | B 14 | | I/O | |
+ * | D7 | B 15 | | I/O | |
+ * | ME | C 13 | P | O | |
+ * | RD | B 0 | P | O | |
+ * | WR | B 1 | P | O | |
+ * | BUSREQ | D 2 | | O | |
+ * | IOCS1 | A 11 | | I | TIM1_CH4 |
+ * | BUSACK | A 12 | | I | |
+ * | HALT | A 12 | | I | |
+ * | NMI | B 7 | | O | |
+ * | RST | B 6 | | O | TIM16_CH1N |
+ * | | | | | |
+ * | | A 9 | | | af1 USART1_TX |
+ * | | A 10 | | | af1 USART1_RX |
+ * | | A 15 | | JTDI | remap SPI1_NSS' |
+ * | | B 3 | | JTDO | remap SPI1_SCK' |
+ * | | B 4 | |NJTRST | remap SPI1_MISO' |
+ * | | B 5 | | | remap SPI1_MOSI' |
+ * | | C 14 | | | af1 OSC32 |
+ * | | C 15 | | | af1 OSC32 |
+
+
+AFIO_MAPR2 =
+AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees
+AFIO_MAPR_SPI1_REMAP
+
+ */
+
/**
*
* Pin assignments
AFIO_MAPR2 =
-AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees
-AFIO_MAPR_SPI1_REMAP
+AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees
+AFIO_MAPR_SPI1_REMAP
*/
#define IOFIELD_GET(src, width, shift) \
((src>>shift) & MASK(width))
-
+
#define CNF_MODE_I_F (GPIO_CNF_INPUT_FLOAT<<2 |GPIO_MODE_INPUT)
#define CNF_MODE_O_PP (GPIO_CNF_OUTPUT_PUSHPULL<<2 | GPIO_MODE_OUTPUT_10_MHZ)
{
RCC_APB2RSTR |= RCC_APB2RSTR_TIM16RST;
RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM16RST;
-
+
TIM16_BDTR = TIM_BDTR_MOE;
-
+
TIM16_CCMR1 = 0
- | TIM_CCMR1_OC1M_FORCE_LOW
+ | TIM_CCMR1_OC1M_FORCE_LOW
| TIM_CCMR1_CC1S_OUT;
-
+
TIM16_CCER = TIM_CCER_CC1NE
| TIM_CCER_CC1NP;
-
+
TIM16_ARR = 48; /* default */
TIM16_CCR1 = 1; /* */
}
static void tim16_set(int mode)
{
uint16_t cc_mode;
-
+
cc_mode = TIM_CCMR1_CC1S_OUT;
TIM16_CR1 = TIM_CR1_OPM;
TIM16_ARR = mode;
cc_mode |= TIM_CCMR1_OC1M_PWM2;
}
-
+
TIM16_CCMR1 = cc_mode;
-
+
if (mode > 0)
TIM16_CR1 |= TIM_CR1_CEN;
}
-/*
+/*
* A0..A6, A8..A13 are buffered. No need to disable.
* A7, A14..A18: set to input.
*/
-
+
static void z80_setup_adrbus_tristate(void)
{
#if 0
gpio_set_mode(ADunbuff1_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, MASK(ADunbuff1_WIDTH) << ADunbuff1_SHIFT);
- gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT,
+ gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT,
(MASK(ADunbuff2_WIDTH) << ADunbuff2_SHIFT) | (MASK(ADunbuff3_WIDTH) << ADunbuff3_SHIFT));
#else
- GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0)))
+ GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0)))
| (CNF_MODE_I_F << (4 * 0));
GPIO_CRL(GPIOC) = (GPIO_CRL(GPIOC) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7))))
| ((CNF_MODE_I_F << (4 * 6)) | (CNF_MODE_I_F << (4 * 7)));
GPIO_CRH(GPIOC) = (GPIO_CRH(GPIOC) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4))))
| ((CNF_MODE_I_F << (4*2)) | (CNF_MODE_I_F << (4*3)) | (CNF_MODE_I_F << (4*4)));
-#endif
+#endif
}
-
+
static void z80_setup_adrbus_active(void)
{
#if 0
gpio_set_mode(ADunbuff1_PORT, GPIO_MODE_OUTPUT_10_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, MASK(ADunbuff1_WIDTH) << ADunbuff1_SHIFT);
- gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,
+ gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,
(MASK(ADunbuff2_WIDTH) << ADunbuff2_SHIFT) | (MASK(ADunbuff3_WIDTH) << ADunbuff3_SHIFT));
#else
- GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0)))
+ GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0)))
| (CNF_MODE_O_PP << (4 * 0));
GPIO_CRL(GPIOC) = (GPIO_CRL(GPIOC) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7))))
| ((CNF_MODE_O_PP << (4 * 6)) | (CNF_MODE_O_PP << (4 * 7)));
GPIO_CRH(GPIOC) = (GPIO_CRH(GPIOC) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4))))
| ((CNF_MODE_O_PP << (4*2)) | (CNF_MODE_O_PP << (4*3)) | (CNF_MODE_O_PP << (4*4)));
-#endif
+#endif
}
void z80_reset(level_t level)
{
int x = level ? -1 : 0;
-
+
tim16_set(x);
-
+
// Z80_O_RST = level;
}
void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length)
{
uint8_t data;
-
+
z80_setup_dbus_out();
Z80_O_ME = 0;
while(length--) {
017B' rx.out_idx: ds 1 ;
017C' rx.buf: ds rx.buf_len ;
018B' rx.buf_end equ $-1 ; last byte (start+len-1)
-
+
018C' tx.bs_mask: ds 1 ; (buf_len - 1)
018D' tx.in_idx: ds 1 ;
018E' tx.out_idx: ds 1 ;
idx_in,
mask;
} fifo_dsc[NUM_FIFOS];
-
+
void z80_memfifo_init(const fifo_t f, uint32_t adr)
{
int z80_memfifo_is_full(const fifo_t f)
{
int rc = 1;
-
+
if (fifo_dsc[f].base != 0) {
z80_request_bus();
rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
uint8_t z80_memfifo_getc(const fifo_t f)
{
uint8_t rc, idx;
-
+
while (z80_memfifo_is_empty(f))
;
fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
z80_release_bus();
-
+
return rc;
}
void z80_memfifo_putc(fifo_t f, uint8_t val)
{
int idx;
-
+
while (z80_memfifo_is_full(f))
;
int z80_msg_fifo_getc(void)
{
int c = -1;
-
+
if (msg_fifo.count != (NELEMS(msg_fifo.buf) - DMA1_CNDTR4)) {
c = msg_fifo.buf[msg_fifo.count];
if (++msg_fifo.count == NELEMS(msg_fifo.buf))
projects / z180-stamp.git / blobdiff