--- /dev/null
+ page 255\r
+ .z80\r
+ \r
+ global f.init,f.in,f.out,f.i.st\r
+\r
+ extrn buf.init\r
+\r
+ include config.inc\r
+ include z180reg.inc\r
+\r
+\r
+;--------------------------------------------------------------\r
+\r
+ dseg\r
+ \r
+\r
+ mkbuf rx.buf,rx.buf_len\r
+ mkbuf tx.buf,tx.buf_len\r
+\r
+\r
+;--------------------------------------------------------------\r
+\r
+ cseg\r
+;\r
+; FIFO channels for communication with stm32\r
+;\r
+; Init Serial I/O for console input and output\r
+;\r
+ \r
+f.init:\r
+ ld ix,rx.buf\r
+ ld a,rx.buf.mask\r
+ call buf.init\r
+ ld ix,tx.buf\r
+ ld a,tx.buf.mask\r
+ jp buf.init\r
+\r
+\r
+f.i.st:\r
+ push ix\r
+ ld ix,rx.buf ;\r
+\r
+buf.empty:\r
+ ld a,(ix+o.in_idx) ;\r
+ sub (ix+o.out_idx) ;\r
+ pop ix\r
+ ret z\r
+ or 0ffh\r
+ ret\r
+ \r
+\r
+f.in:\r
+ push ix\r
+ ld ix,rx.buf ;\r
+\r
+buf.get:\r
+ ld a,(ix+o.out_idx) ;\r
+bg.wait:\r
+ cp (ix+o.in_idx) ;\r
+ jr z,bg.wait\r
+\r
+ push hl ;\r
+ push ix\r
+ pop hl\r
+ add a,l\r
+ ld l,a\r
+ jr nc,bg.nc\r
+ inc h\r
+bg.nc:\r
+ ld l,(hl)\r
+ \r
+ ld a,(ix+o.out_idx) ;\r
+ inc a\r
+ and (ix+o.mask)\r
+ ld (ix+o.out_idx),a\r
+ \r
+ ld a,l\r
+ pop hl\r
+ pop ix\r
+ ret\r
+\r
+\r
+f.o.st:\r
+ push ix\r
+ ld ix,tx.buf ;\r
+\r
+buf.full:\r
+ ld a,(ix+o.in_idx) ;\r
+ inc a\r
+ and (ix+o.mask)\r
+ sub (ix+o.out_idx) ;\r
+ pop ix\r
+ ret z\r
+ or 0ffh\r
+ ret\r
+\r
+\r
+f.out:\r
+ push ix\r
+ ld ix,tx.buf ;\r
+\r
+buf.put:\r
+ push hl ;\r
+ push bc\r
+ push ix\r
+ pop hl\r
+ ld c,(ix+o.in_idx) ;\r
+ ld b,0\r
+ add hl,bc\r
+ ld b,a\r
+\r
+ ld a,c ;\r
+ inc a\r
+ and (ix+o.mask)\r
+bp.wait:\r
+ cp (ix+o.out_idx) ;\r
+ jr z,bp.wait\r
+ ld (hl),b\r
+ ld (ix+o.in_idx),a\r
+ \r
+ ld a,b\r
+ pop bc\r
+ pop hl\r
+ pop ix\r
+ ret\r
+\r
+ end\r
+\r