b2m FE,4 ;Framing Error\r
b2m RIE,3 ;Receive Interrupt Enable\r
b2m DCD0,2 ;Data Carrier Detect (Ch 0)\r
- b2m CTS1E,2 ;Clear To Send (Ch 1)\r
+ b2m CTS1E,2 ;Clear To Send Enable (Ch 1)\r
b2m TDRE,1 ;Transmit Data Register Empty\r
b2m TIE,0 ;Transmit Interrupt Enable\r
\r
dstat equ IOBASE+30h ;DMA Status Register\r
b2m DE1,7 ;DMA enable ch 1,0\r
b2m DE0,6 ;\r
- b2m DWE1,5 ;DMA Enable Bit Write Enable 1,0\r
- b2m DWE0,4 ;\r
+ b2m NDWE1,5 ;DMA Enable Bit Write Enable 1,0\r
+ b2m NDWE0,4 ;\r
b2m DIE1,3 ;DMA Interrupt Enable 1,0\r
b2m DIE0,2 ;\r
b2m DME,0 ;DMA Master enable\r
IV$ASCI1 equ 16 ;ASCI channel 1 (lowest priority)\r
\r
.list\r
-\r