- * | A0 | PA 0 | O | |
- * | A1 | PA 1 | O | |
- * | A2 | PA 2 | O | |
- * | A3 | PA 3 | O | |
- * | A4 | PA 4 | O | |
- * | A5 | PA 5 | O | |
- * | A6 | PA 6 | O | |
- * | A7 | PA 7 | O | |
- * | A8 | PC 0 | O | |
- * | A9 | PC 1 | O | |
- * | A10 | PC 2 | O | |
- * | A11 | PC 3 | O | |
- * | A12 | PC 4 | O | |
- * | A13 | PC 5 | O | |
- * | A14 | PC 6 | O | |
- * | A15 | PC 7 | O | |
- * | A16 | PE 2 | O | |
- * | A17 | PE 3 | O | |
- * | A18 | PE 4 | O | |
- * | D0 | PF 0 | I/O | |
- * | D1 | PF 1 | I/O | |
- * | D2 | PF 2 | I/O | |
- * | D3 | PF 3 | I/O | |
- * | D4 | PF 4 | I/O | |
- * | D5 | PF 5 | I/O | |
- * | D6 | PF 6 | I/O | |
- * | D7 | PF 7 | I/O | |
- * | RD | PD 3 | O | |
- * | WR | PD 2 | O | |
- * | MREQ | PD 4 | O | |
- * | RST | PD 5 | O | |
- * | BUSREQ | PD 7 | O | |
- * | BUSACK | PD 6 | I | |
- * | IOCS1 | PE 5 | I | |
- * |* HALT | P | | |
- * |* NMI | P | | |
- * | | P | | |
- * | | P | | af1 USART1_TX |
- * | | P | | af1 USART1_RX |
- * | | P |JTDI | remap SPI1_NSS' |
- * | | P |JTDO | remap SPI1_SCK' |
- * | | P |JTRST | remap SPI1_MISO' |
- * | | P | | remap SPI1_MOSI' |
- * | | P | | af1 OSC32 |
- * | | P | | af1 OSC32 |
+ * | A0 | PA 0 | O | |
+ * | A1 | PA 1 | O | |
+ * | A2 | PA 2 | O | |
+ * | A3 | PA 3 | O | |
+ * | A4 | PA 4 | O | |
+ * | A5 | PA 5 | O | |
+ * | A6 | PA 6 | O | |
+ * | A7 | PA 7 | O | |
+ * | A8 | PC 0 | O | |
+ * | A9 | PC 1 | O | |
+ * | A10 | PC 2 | O | |
+ * | A11 | PC 3 | O | |
+ * | A12 | PC 4 | O | |
+ * | A13 | PC 5 | O | |
+ * | A14 | PC 6 | O | |
+ * | A15 | PC 7 | O | |
+ * | A16 | PE 2 | O | |
+ * | A17 | PE 3 | O | |
+ * | A18 | PE 4 | O | |
+ * | D0 | PF 0 | I/O | |
+ * | D1 | PF 1 | I/O | |
+ * | D2 | PF 2 | I/O | |
+ * | D3 | PF 3 | I/O | |
+ * | D4 | PF 4 | I/O | |
+ * | D5 | PF 5 | I/O | |
+ * | D6 | PF 6 | I/O | |
+ * | D7 | PF 7 | I/O | |
+ * | RD | PD 3 | O | |
+ * | WR | PD 2 | O | |
+ * | MREQ | PD 4 | O | |
+ * | RST | PD 5 | O | |
+ * | BUSREQ | PD 7 | O | |
+ * | BUSACK | PD 6 | I | |
+ * | IOCS1 | PE 5 | I | |
+ * |* HALT | P | | |
+ * |* NMI | P | | |
+ * | | P | | |
+ * | | P | | af1 USART1_TX |
+ * | | P | | af1 USART1_RX |
+ * | | P |JTDI | remap SPI1_NSS' |
+ * | | P |JTDO | remap SPI1_SCK' |
+ * | | P |JTRST | remap SPI1_MISO' |
+ * | | P | | remap SPI1_MOSI' |
+ * | | P | | af1 OSC32 |
+ * | | P | | af1 OSC32 |
-/* Number of array elements */
-#define NELEMS(x) (sizeof x/sizeof *x)
-
-struct bits {
- uint8_t b0:1;
- uint8_t b1:1;
- uint8_t b2:1;
- uint8_t b3:1;
- uint8_t b4:1;
- uint8_t b5:1;
- uint8_t b6:1;
- uint8_t b7:1;
-} __attribute__((__packed__));
-
-typedef struct bits pbit_t;
-
-#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
-
#define MASK(n) ((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))
#define MASK(n) ((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))
+static volatile uint8_t timer; /* used for bus timeout */
+
+/*---------------------------------------------------------*/
+/* 10Hz timer interrupt generated by OC4A */
+/*---------------------------------------------------------*/
+
+ISR(TIMER4_COMPA_vect)
+{
+
+ uint8_t i = timer;
+
+ if (i)
+ timer = i - 1;
+}
Z80_O_BUSREQ = 1;
Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
}
if (zstate & ZST_ACQUIRED) {
Z80_O_BUSREQ = 1;
Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
}
if (zstate & ZST_ACQUIRED) {
- z80_bus_cmd(Request);
-
- fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
- fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
- fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);
-
- z80_bus_cmd(Release);
+ z80_bus_cmd(Request);
+ fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
+ fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
+ fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
+ z80_bus_cmd(Release);
+ }