+/*
+ * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
/**
*
* Pin assignments
*
- * | Z180-Sig | AVR-Port | Dir | Special Function |
- * +------------+---------------+-------+-----------------------+
- * | A0 | PA 0 | O | |
- * | A1 | PA 1 | O | |
- * | A2 | PA 2 | O | |
- * | A3 | PA 3 | O | |
- * | A4 | PA 4 | O | |
- * | A5 | PA 5 | O | |
- * | A6 | PA 6 | O | |
- * | A7 | PA 7 | O | |
- * | A8 | PC 0 | O | |
- * | A9 | PC 1 | O | |
- * | A10 | PC 2 | O | |
- * | A11 | PC 3 | O | |
- * | A12 | PC 4 | O | |
- * | A13 | PC 5 | O | |
- * | A14 | PC 6 | O | |
- * | A15 | PC 7 | O | |
- * | A16 | PE 2 | O | |
- * | A17 | PE 3 | O | |
- * | A18 | PE 4 | O | |
- * | D0 | PF 0 | I/O | |
- * | D1 | PF 1 | I/O | |
- * | D2 | PF 2 | I/O | |
- * | D3 | PF 3 | I/O | |
- * | D4 | PF 4 | I/O | |
- * | D5 | PF 5 | I/O | |
- * | D6 | PF 6 | I/O | |
- * | D7 | PF 7 | I/O | |
- * | RD | PD 3 | O | |
- * | WR | PD 2 | O | |
- * | MREQ | PD 4 | O | |
- * | RST | PD 5 | O | |
- * | BUSREQ | PD 7 | O | |
- * | BUSACK | PD 6 | I | |
- * | IOCS1 | PE 5 | I | |
- * |* HALT | P | | |
- * |* NMI | P | | |
- * | | P | | |
- * | | P | | af1 USART1_TX |
- * | | P | | af1 USART1_RX |
- * | | P |JTDI | remap SPI1_NSS' |
- * | | P |JTDO | remap SPI1_SCK' |
- * | | P |JTRST | remap SPI1_MISO' |
- * | | P | | remap SPI1_MOSI' |
- * | | P | | af1 OSC32 |
- * | | P | | af1 OSC32 |
-
+ * | Z180-Sig | AVR-Port | Dir |
+ * +------------+---------------+-------+
+ * | A0 | PA 0 | O |
+ * | A1 | PA 1 | O |
+ * | A2 | PA 2 | O |
+ * | A3 | PA 3 | O |
+ * | A4 | PA 4 | O |
+ * | A5 | PA 5 | O |
+ * | A6 | PA 6 | O |
+ * | A7 | PA 7 | O |
+ * | A8 | PC 0 | O |
+ * | A9 | PC 1 | O |
+ * | A10 | PC 2 | O |
+ * | A11 | PC 3 | O |
+ * | A12 | PC 4 | O |
+ * | A13 | PC 5 | O |
+ * | A14 | PC 6 | O |
+ * | A15 | PC 7 | O |
+ * | A16 | PE 2 | O |
+ * | A17 | PE 3 | O |
+ * | A18 | PE 4 | O |
+ * | D0 | PF 0 | I/O |
+ * | D1 | PF 1 | I/O |
+ * | D2 | PF 2 | I/O |
+ * | D3 | PF 3 | I/O |
+ * | D4 | PF 4 | I/O |
+ * | D5 | PF 5 | I/O |
+ * | D6 | PF 6 | I/O |
+ * | D7 | PF 7 | I/O |
+ * | RD | PD 3 | O |
+ * | WR | PD 2 | O |
+ * | MREQ | PD 4 | O |
+ * | RST | PD 5 | O |
+ * | BUSREQ | PD 7 | O |
+ * | BUSACK | PD 6 | I |
+ * |
+ * | Optional
+ * +------------------------------------+
+ * | STEP | PG 0 | O |
+ * | RUN | PG 1 | O |
+ * | WAIT | PG 2 | I |
*/
-#include <avr/io.h>
+
+#include "z80-if.h"
#include <util/atomic.h>
-#include <stdio.h>
#include "debug.h"
-#include "z80-if.h"
-
-
-/* Number of array elements */
-#define NELEMS(x) (sizeof x/sizeof *x)
-
-struct bits {
- uint8_t b0:1;
- uint8_t b1:1;
- uint8_t b2:1;
- uint8_t b3:1;
- uint8_t b4:1;
- uint8_t b5:1;
- uint8_t b6:1;
- uint8_t b7:1;
-} __attribute__((__packed__));
-
-typedef struct bits pbit_t;
-
-#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
+#include "config.h"
+#include "env.h"
//#define P_ZCLK PORTB
#define WR 2
#define P_BUSREQ PORTD
#define BUSREQ 7
+#define PIN_BUSREQ PIND
#define DDR_BUSREQ DDRD
#define P_BUSACK PORTD
#define PIN_BUSACK PIND
#define BUSACK 6
#define DDR_BUSACK DDRD
-//#define P_HALT PORTA
-//#define HALT 12
-#define P_IOCS1 PORTE
-#define IOCS1 5
-#define DDR_IOCS1 DDRE
-//#define P_NMI PORTB
-//#define NMI 7
#define P_RST PORTD
+#define PIN_RST PIND
#define DDR_RST DDRD
#define RST 5
#define Z80_O_RD SBIT(P_RD, 3)
#define Z80_O_WR SBIT(P_WR, 2)
#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
+#define Z80_I_BUSREQ SBIT(PIN_BUSREQ, 7)
//#define Z80_O_NMI SBIT(P_NMI, )
#define Z80_O_RST SBIT(P_RST, 5)
+#define Z80_I_RST SBIT(PIN_RST, 5)
#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT SBIT(P_HALT, )
+/* Optional */
+#define P_RUN PORTG
+#define RUN 1
+#define DDR_RUN DDRG
+#define P_STEP PORTG
+#define STEP 0
+#define DDR_STEP DDRG
+#define P_WAIT PORTG
+#define WAIT 2
+#define DDR_WAIT DDRG
+/* All three signals are on the same Port (PortG) */
+#define PORT_SS PORTG
+#define DDR_SS DDRG
+#define PIN_SS PING
+#define Z80_O_RUN SBIT(PORT_SS, RUN)
+#define Z80_O_STEP SBIT(PORT_SS, STEP)
+#define Z80_I_WAIT SBIT(PORT_SS, WAIT)
+
+
+#define BUS_TO 20
+
#define MASK(n) ((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))
+void z80_bus_request_or_exit(void)
+{
+ if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
+ cmd_error(CMD_RET_FAILURE, EBUSTO, NULL);
+}
+
+static zstate_t zstate;
+static volatile uint8_t timer; /* used for bus timeout */
-typedef union {
- uint32_t l;
- uint16_t w[2];
- uint8_t b[4];
-} addr_t;
+static volatile uint16_t busack_cycles_ovl;
-static zstate_t zstate;
+static uint32_t busack_cycles;
+
+ISR(TIMER4_COMPB_vect)
+{
+ busack_cycles_ovl++;
+}
+
+/*---------------------------------------------------------*/
+/* 10Hz timer interrupt generated by OC5A */
+/*---------------------------------------------------------*/
+
+ISR(TIMER5_COMPA_vect)
+{
+ uint8_t i = timer;
+
+ if (i)
+ timer = i - 1;
+}
/*--------------------------------------------------------------------------*/
-static void z80_addrbus_set_tristate(void)
+static void z80_addrbus_set_in(void)
{
/* /MREQ, /RD, /WR: Input, no pullup */
DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
DDR_ADL = 0;
P_ADH = 0;
DDR_ADH = 0;
- PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
+ PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT);
DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
}
-static void z80_addrbus_set_active(void)
+static void z80_addrbus_set_out(void)
{
/* /MREQ, /RD, /WR: Output and high */
Z80_O_MREQ = 1;
DDR_DB = 0xff;
}
+static void z80_reset_active(void)
+{
+ if (Stat & S_RESET_POLARITY)
+ Z80_O_RST = 1;
+ else
+ Z80_O_RST = 0;
+}
+
+static void z80_reset_inactive(void)
+{
+ if (Stat & S_RESET_POLARITY)
+ Z80_O_RST = 0;
+ else
+ Z80_O_RST = 1;
+}
static void z80_reset_pulse(void)
{
- Z80_O_RST = 0;
+ z80_reset_active();
_delay_us(10);
- Z80_O_RST = 1;
+ z80_reset_inactive();
}
void z80_setup_bus(void)
{
- /* /ZRESET: Output and low */
- Z80_O_RST = 0;
- DDR_RST |= _BV(RST);
+ ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
+
+ /* /ZRESET: Input, no pullup */
+ DDR_RST &= ~_BV(RST);
+ Z80_O_RST = 0;
- /* /BUSREQ: Output and high */
- Z80_O_BUSREQ = 1;
- DDR_BUSREQ |= _BV(BUSREQ);
+ /* /BUSREQ: Output and high */
+ Z80_O_BUSREQ = 1;
+ DDR_BUSREQ |= _BV(BUSREQ);
- /* /BUSACK: Input, no pullup */
- DDR_BUSACK &= ~_BV(BUSACK);
- P_BUSACK &= ~_BV(BUSACK);
+ /* /BUSACK: Input, no pullup */
+ DDR_BUSACK &= ~_BV(BUSACK);
+ P_BUSACK &= ~_BV(BUSACK);
- /* /IOCS1: Input, no pullup */
- DDR_IOCS1 &= ~_BV(IOCS1);
- P_IOCS1 &= ~_BV(IOCS1);
+ z80_addrbus_set_in();
+ z80_dbus_set_in();
- z80_addrbus_set_tristate();
- z80_dbus_set_in();
+ if (getenv_yesno(PSTR(ENV_SINGLESTEP))) {
+ /* /RUN & /STEP: output, /WAIT: input */
+
+ PORT_SS = (PORT_SS & ~_BV(RUN)) | _BV(STEP);
+ DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
+ }
+
+ if (Z80_I_RST)
+ Stat |= S_RESET_POLARITY;
+ else
+ Stat &= ~S_RESET_POLARITY;
+ z80_reset_active();
+ DDR_RST |= _BV(RST);
+
+ zstate = RESET;
+ }
+
+ /* Timer 5 */
+ PRR1 &= ~_BV(PRTIM5);
+ OCR5A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
+ TCCR5B = (0b01<<WGM52)|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */
+ TIMSK5 = _BV(OCIE5A); /* Enable oca interrupt */
- zstate = RESET;
}
+uint32_t z80_get_busreq_cycles(void)
+{
+ return busack_cycles;
+}
+
zstate_t z80_bus_state(void)
{
return zstate;
}
+void z80_toggle_reset(void)
+{
+ Z80_I_RST = 1;
+}
+
+void z80_toggle_busreq(void)
+{
+ Z80_I_BUSREQ = 1;
+}
+
static void z80_busreq_hpulse(void)
{
z80_dbus_set_in();
- z80_addrbus_set_tristate();
+ z80_addrbus_set_in();
+#if 0
ATOMIC_BLOCK(ATOMIC_FORCEON) {
Z80_O_BUSREQ = 1;
Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
}
+#endif
+
+#if 1
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ Z80_O_BUSREQ = 1;
+
+ do {
+ if (Z80_I_BUSACK == 1) {
+ Z80_O_BUSREQ = 0;
+ break;
+ }
+ } while (1);
+ }
+#endif
if (zstate & ZST_ACQUIRED) {
- while(Z80_I_BUSACK == 1)
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 1 && timer)
;
- z80_addrbus_set_active();
+ if (Z80_I_BUSACK == 0)
+ z80_addrbus_set_out();
}
}
/*
- + | | | | |
+ + | | | | |
+ State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
- + | | | | |
- + | 0 | 1 | 2 | 3 |
-Event + | | | | |
+ + | | | | |
+ + | 0 | 1 | 2 | 3 |
+Event + | | | | |
----------------+---------------+---------------+---------------+---------------+
- | | | | |
-Reset | 0 | 0 | 0 | 0 |
- | | | | |
- | | | | |
-Request | 1 | | 3 | |
- | | | | |
- | | | | |
-Release | | 0 | | 2 |
- | | | | |
- | | | | |
-Run | 2 | 3 | | |
- | | | | |
- | | | | |
-Restart | | | 2 | 3 |
- | | | | |
- | | | | |
-M_Cycle | | | | 3 |
- | | | | |
- | | | | |
+ | | | | |
+Reset | 0 | 0 | 0 | 0 |
+ | | | | |
+ | | | | |
+Request | 1 | | 3 | |
+ | | | | |
+ | | | | |
+Release | | 0 | | 2 |
+ | | | | |
+ | | | | |
+Run | 2 | 3 | | |
+ | | | | |
+ | | | | |
+Restart | | | 2 | 3 |
+ | | | | |
+ | | | | |
+M_Cycle | | | | 3 |
+ | | | | |
+ | | | | |
*/
zstate_t z80_bus_cmd(bus_cmd_t cmd)
case Reset:
z80_dbus_set_in();
- z80_addrbus_set_tristate();
- Z80_O_RST = 0;
+ z80_addrbus_set_in();
+ z80_reset_active();
+ _delay_us(10);
Z80_O_BUSREQ = 1;
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 0 && timer)
+ ;
zstate = RESET;
break;
switch (zstate) {
case RESET:
Z80_O_BUSREQ = 0;
- Z80_O_RST = 1;
- while(Z80_I_BUSACK == 1)
+ timer = 255; //BUS_TO;
+
+ uint16_t tcnt;
+ uint16_t ovl_cnt;
+ uint8_t ifr;
+ busack_cycles = 0;
+ busack_cycles_ovl = 0;
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ Z80_I_RST = 1; /* Toggle RESET --> inactive */
+ OCR4B = TCNT4;
+ TIFR4 = _BV(OCF4B); /* Clear compare match flag */
+// TIMSK4 &= ~_BV(OCIE4A); /* Disable Output Compare A interrupt */
+ }
+ TIMSK4 |= _BV(OCIE4B); /* Enable compare match interrupt */
+
+ while (Z80_I_BUSACK == 1 && timer)
;
- z80_addrbus_set_active();
- zstate = RESET_AQRD;
+
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ tcnt = TCNT4 - OCR4B;
+ ovl_cnt = busack_cycles_ovl;
+ ifr = TIFR4;
+ TIMSK4 &= ~_BV(OCIE4B); /* Disable compare match interrupt */
+// TIMSK4 |= _BV(OCIE4A); /* Enable Output Compare A interrupt */
+ }
+ if (Z80_I_BUSACK == 0) {
+ if ((ifr & _BV(OCF4B)) && !(tcnt & (1<<15)))
+ ovl_cnt++;
+ busack_cycles = tcnt + ((uint32_t) ovl_cnt << 16);
+ z80_addrbus_set_out();
+ zstate = RESET_AQRD;
+// debug("### ovl: %u, ifr: %u, beg: %u, end: %u\n", ovl_cnt,
+// (ifr & _BV(OCF4B)) != 0, OCR4B, tcnt);
+ } else {
+ z80_reset_active();
+ Z80_O_BUSREQ = 1;
+ }
break;
case RUNNING:
Z80_O_BUSREQ = 0;
- while(Z80_I_BUSACK == 1)
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 1 && timer)
;
- z80_addrbus_set_active();
- zstate = RUNNING_AQRD;
+ if (Z80_I_BUSACK == 0) {
+ z80_addrbus_set_out();
+ zstate = RUNNING_AQRD;
+ } else {
+ Z80_O_BUSREQ = 1;
+ }
break;
default:
switch (zstate) {
case RESET_AQRD:
z80_dbus_set_in();
- z80_addrbus_set_tristate();
- Z80_O_RST = 0;
+ z80_addrbus_set_in();
+ z80_reset_active();
+ _delay_us(10);
Z80_O_BUSREQ = 1;
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 0 && timer)
+ ;
zstate = RESET;
break;
case RUNNING_AQRD:
z80_dbus_set_in();
- z80_addrbus_set_tristate();
+ z80_addrbus_set_in();
Z80_O_BUSREQ = 1;
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 0 && timer)
+ ;
zstate = RUNNING;
break;
default:
case Run:
switch (zstate) {
case RESET:
- Z80_O_RST = 1;
+ _delay_ms(20); /* TODO: */
+ z80_reset_inactive();
zstate = RUNNING;
break;
case RESET_AQRD:
z80_dbus_set_in();
- z80_addrbus_set_tristate();
+ z80_addrbus_set_in();
z80_reset_pulse();
- z80_addrbus_set_active();
+ z80_addrbus_set_out();
zstate = RUNNING_AQRD;
break;
default:
case M_Cycle:
switch (zstate) {
case RUNNING_AQRD:
- z80_busreq_hpulse();
+ z80_busreq_hpulse(); /* TODO: */
break;
default:
break;
return zstate;
}
+/*--------------------------------------------------------------------------*/
+
+#define DEBUG_FREQ 0 /* set to 1 to debug */
+
+#define debug_cpu(fmt, args...) \
+ debug_cond(DEBUG_FREQ, fmt, ##args)
+
+#if 0
+static
+char * ulltoa (uint64_t val, char *s)
+{
+ char *p = s;
+
+ while (val >= 10) {
+ *p++ = (val % 10) + '0';
+ val = val / 10;
+ }
+ *p++ = val + '0';
+ *p = '\0';
+
+ return strrev(s);
+}
+#endif
+
+uint32_t z80_measure_phi(uint_fast8_t cycles)
+{
+ uint16_t ref_stop;
+ uint16_t ref_ovfl;
+ uint8_t x_ovfl;
+ uint32_t x_freq;
+
+
+ PRR1 &= ~_BV(PRTIM3);
+ TCCR3A = 0;
+ TCCR3B = 0b000<<CS30; /* stop counter */
+ TCNT3 = 0;
+ x_ovfl = 0;
+ TIFR3 = _BV(TOV3);
+ ref_ovfl = 0;
+
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ EIFR = _BV(INTF6); /* Reset pending int */
+ while ((EIFR & _BV(INTF6)) == 0) /* Wait for falling edge */
+ ;
+ OCR4B = TCNT4;
+ TCCR3B = 0b110<<CS30; /* Count falling edges on T3 (==INT6) */
+ TIFR4 = _BV(OCF4B); /* clear compare match flag */
+
+ while (ref_ovfl < 60) {
+ if ((TIFR4 & _BV(OCF4B)) != 0) {
+ TIFR4 = _BV(OCF4B);
+ ++ref_ovfl;
+ }
+ if ((TIFR3 & _BV(TOV3)) != 0) {
+ TIFR3 = _BV(TOV3);
+ ++x_ovfl;
+ }
+ }
+
+ EIFR = _BV(INTF6);
+ for (;;) {
+ if (EIFR & _BV(INTF6)) {
+ TCCR3B = 0b000<<CS30; /* stop counter */
+ ref_stop = TCNT4;
+ break;
+ }
+ if ((TIFR4 & _BV(OCF4B)) != 0) {
+ TIFR4 = _BV(OCF4B);
+ ++ref_ovfl;
+ }
+ }
+ }
+
+ if ((TIFR3 & _BV(TOV3)) != 0) {
+ TIFR3 = _BV(TOV3);
+ x_ovfl++;
+ }
+
+ uint32_t ref_cnt = (ref_stop - OCR4B) + ((uint32_t)ref_ovfl << 16);
+ uint32_t x_cnt = TCNT3 + ((uint32_t) x_ovfl << 16);
+ uint64_t x_tmp = (uint64_t) 100000 * (x_cnt * cycles);
+
+ /* Stop Timer */
+ TCCR3B = 0;
+ PRR1 |= _BV(PRTIM3);
+
+ debug_cpu("\nx_ovfl: %6u, TCNT3: %6u, cycles: %3u\n", x_ovfl, TCNT3, cycles);
+ debug_cpu("ref_ovfl: %6u, ref_...: %6u\n", ref_ovfl, ref_stop-OCR4B);
+ debug_cpu("x_cnt: %9lu, ref_cnt: %9lu\n", x_cnt, ref_cnt);
+
+ x_tmp = (x_tmp * getenv_ulong(PSTR(ENV_FMON), 10, F_CPU) + (ref_cnt / 2)) / ref_cnt;
+
+ /* round to 5 decimal digits */
+ int_fast8_t sc = 5;
+ for ( ; sc > 0 || x_tmp >= 100000; sc--) x_tmp = (x_tmp + 5)/10;
+ x_freq = x_tmp;
+ for ( ; sc < 0; sc++) x_freq *= 10;
+
+ return x_freq;
+}
/*--------------------------------------------------------------------------*/
//inline __attribute__ ((always_inline))
void z80_setaddress(uint32_t addr)
{
- addr_t x; x.l = addr;
+ P_ADL = addr;
+ P_ADH = (addr & 0xff00) >> 8;
+ PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
+}
+
+int32_t z80_memsize_detect(void)
+{
+ const uint8_t PATTERN_1 = 0x55;
+ const uint8_t PATTERN_2 = ~PATTERN_1;
+ uint32_t addr;
+
+ if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
+ return -EBUSTO;
+
+ uint8_t ram_0 = z80_read(0);
+ uint8_t ram_1 = z80_read(1);
+
+ z80_write(0, ram_0 ^ 0xff);
+ z80_write(1, ram_1);
+ if ((z80_read(0) ^ ram_0) != 0xff) {
+ addr = 0;
+ } else {
+ z80_write(0, PATTERN_1);
+ for (addr=1; addr < CONFIG_SYS_RAMSIZE_MAX; addr <<= 1) {
+ uint8_t ram_i = z80_read(addr);
+ z80_write(addr, PATTERN_2);
+ if (z80_read(0) != PATTERN_1 || z80_read(addr) != PATTERN_2)
+ break;
+ z80_write(addr, ram_i);
+ }
+ }
+
+ z80_write(0, ram_0);
+ z80_bus_cmd(Release);
- P_ADL = x.b[0];
- P_ADH = x.b[1];
- PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
+ return addr;
}
+/*--------------------------------------------------------------------------*/
+
void z80_write(uint32_t addr, uint8_t data)
{
z80_setaddress(addr);
{
z80_dbus_set_out();
Z80_O_MREQ = 0;
+ P_DB = data;
while(length--) {
z80_setaddress(addr++);
+ Z80_O_WR = 0;
+ Z80_O_WR = 0;
+ Z80_O_WR = 1;
+ }
+ Z80_O_MREQ = 1;
+}
+
+void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
+{
+ uint8_t data;
+
+ z80_dbus_set_out();
+ Z80_O_MREQ = 0;
+ while(length--) {
+ z80_setaddress(dest++);
+ data = *src++;
P_DB = data;
P_DB = data;
Z80_O_WR = 0;
Z80_O_MREQ = 1;
}
-void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
+void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
{
uint8_t data;
Z80_O_MREQ = 1;
}
+void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
+{
+ uint8_t data;
+
+ Z80_O_MREQ = 0;
+ z80_dbus_set_in();
+ while(length--) {
+ z80_setaddress(src++);
+ Z80_O_RD = 0;
+ Z80_O_RD = 0;
+ Z80_O_RD = 0;
+ data = PIN_DB;
+ Z80_O_RD = 1;
+ *dest++ = data;
+ }
+ Z80_O_MREQ = 1;
+}
+
+/*--------------------------------------------------------------------------*/
+
/*
0179' rx.bs_mask: ds 1 ; (buf_len - 1)
017A' rx.in_idx: ds 1 ;
{
fifo_dsc[f].base = addr;
- if (addr != 0) {
-
-DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
+ if (addr != 0) {
z80_bus_cmd(Request);
fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
z80_bus_cmd(Release);
+
+ if (fifo_dsc[f].idx_in != 0 || fifo_dsc[f].idx_out != 0) {
+ DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
+ f, addr, fifo_dsc[f].idx_in, fifo_dsc[f].idx_out, fifo_dsc[f].mask);
+ }
}
}
int z80_memfifo_is_full(const fifo_t f)
{
- int rc = 1;
+ int rc = 0;
if (fifo_dsc[f].base != 0) {
z80_bus_cmd(Request);
z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
z80_bus_cmd(Release);
}
+
+/*--------------------------------------------------------------------------*/
+
+void z80_load_mem(int_fast8_t verbosity,
+ const FLASH unsigned char data[],
+ const FLASH unsigned long *sections,
+ const FLASH unsigned long address[],
+ const FLASH unsigned long length_of_sections[])
+{
+ uint32_t sec_base = 0;
+
+ if (verbosity > 1)
+ printf_P(PSTR("Loading Z180 memory... \n"));
+
+ for (unsigned sec = 0; sec < *sections; sec++) {
+ if (verbosity > 0) {
+ printf_P(PSTR(" From: 0x%.5lX to: 0x%.5lX (%5li bytes)\n"),
+ address[sec],
+ address[sec]+length_of_sections[sec] - 1,
+ length_of_sections[sec]);
+ }
+
+ z80_write_block_P((const FLASH unsigned char *) &data[sec_base], /* src */
+ address[sec], /* dest */
+ length_of_sections[sec]); /* len */
+ sec_base += length_of_sections[sec];
+ }
+}