Remove memory test and bank manager.

[z180-stamp.git] / z180 / config.inc

diff --git a/z180/config.inc b/z180/config.inc
index 390d3bc9cf1b64595a83e5ef16b112129c3c2e33..ed98656c936f9214df8b2fd109f3b7579167647b 100644 (file)
--- a/z180/config.inc
+++ b/z180/config.inc
@@ -1,13 +1,19 @@
+\r
+FALSE  equ     0\r
+TRUE   equ     NOT FALSE\r
+\r
 ;-----------------------------------------------------\r
 ; CPU and BANKING types\r
 \r
 \r
-CPU_Z180       equ     1               ; 0 = Z80, else Z180\r
-ROMSYS         equ     0\r
+CPU_Z180       equ     TRUE\r
+CPU_Z80                equ     FALSE\r
+\r
+ROMSYS         equ     FALSE\r
 \r
 AVRCLK         equ     18432           ;[KHz]\r
 \r
-       if CPU_Z180\r
+    if CPU_Z180\r
 \r
 ;-----------------------------------------------------\r
 FOSC           equ     AVRCLK/2        ;Oscillator frequency [KHz]\r
@@ -26,8 +32,21 @@ PRT_TC10MS   equ     PHI / (PRT_PRE/10)
 ;-----------------------------------------------------\r
 ; MMU\r
 \r
-SYS$CBAR       equ     0C8h\r
-USR$CBAR       equ     0F0h\r
+COMMON_SIZE    equ     4*1024          ;Common Area size in bytes\r
+                                       ;must be multiple of 4K\r
+\r
+if (COMMON_SIZE mod 1000h) \r
+       .printx COMMON_SIZE not multiple of 4K!\r
+       end     ;stop assembly\r
+endif\r
+\r
+CSK    equ     COMMON_SIZE/1000h       ;\r
+CA     equ     10h - CSK               ;common area start\r
+BA     equ     0                       ;banked area start\r
+\r
+SYS$CBR                equ     0\r
+SYS$CBAR       equ     CA<<4 + CA      ;CBAR in system mode\r
+USR$CBAR       equ     CA<<4 + BA      ;CBAR in user mode (CP/M)\r
 \r
 \r
 BANKS          equ     18              ;max nr. of banks\r
@@ -37,7 +56,8 @@ BANKS         equ     18              ;max nr. of banks
 CREFSH         equ     0               ;Refresh rate register (disable refresh)\r
 CWAITIO                equ     3 shl IWI0      ;Max I/O Wait States, 0 Memory Wait States\r
 \r
-       else    ; Z80\r
+    endif              ;CPU_Z180\r
+    if CPU_Z80\r
 \r
 PHI            equ     AVRCLK/5        ;CPU frequency [KHz]\r
 BAUDCLCK       equ     AVRCLK/10       ;Baudrate clock [KHz]\r
@@ -71,16 +91,16 @@ CTC3        EQU     0f7h
 ;    600       3072     16     192\r
 ;    300       6144     64      92\r
 \r
-       endif   ; CPU_Z180\r
+    endif      ; CPU_Z80\r
 \r
-       if      ROMSYS\r
+    if ROMSYS\r
 c$rom          equ     0a5h\r
 ROM_EN         equ     0C0h\r
 ROM_DIS                equ     ROMEN+1\r
-       if CPU_Z180\r
+     if CPU_Z180\r
 CWAITROM       equ     2 shl MWI0\r
-       endif\r
-       endif\r
+     endif\r
+    endif\r
 \r
 \r
 DRSTNUM        equ     30h             ;DDTZ Restart vector (breakpoints)\r
@@ -100,7 +120,7 @@ AVRINT6             equ     5Fh
 ;PMSG          equ     80h\r
 \r
 ;-----------------------------------------------------\r
-; Definition of (locical) top 2 memory pages\r
+; Definition of (logical) top 2 memory pages\r
 \r
 sysram_start   equ     0FE00h\r
 stacksize      equ     80\r