#define BUSACK 6
#define DDR_BUSACK DDRD
#define P_RST PORTD
+#define PIN_RST PIND
#define DDR_RST DDRD
#define RST 5
#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
//#define Z80_O_NMI SBIT(P_NMI, )
#define Z80_O_RST SBIT(P_RST, 5)
+#define Z80_I_RST SBIT(PIN_RST, 5)
#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT SBIT(P_HALT, )
static zstate_t zstate;
static volatile uint8_t timer; /* used for bus timeout */
+static bool reset_polarity;
/*---------------------------------------------------------*/
/* 10Hz timer interrupt generated by OC4A */
DDR_DB = 0xff;
}
+static void z80_reset_active(void)
+{
+ if (reset_polarity)
+ Z80_O_RST = 1;
+ else
+ Z80_O_RST = 0;
+}
+
+static void z80_reset_inactive(void)
+{
+ if (reset_polarity)
+ Z80_O_RST = 0;
+ else
+ Z80_O_RST = 1;
+}
static void z80_reset_pulse(void)
{
- Z80_O_RST = 0;
+ z80_reset_active();
_delay_us(10);
- Z80_O_RST = 1;
+ z80_reset_inactive();
}
{
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
- /* /ZRESET: Output and low */
+ /* /ZRESET: Input, no pullup */
+ DDR_RST &= ~_BV(RST);
Z80_O_RST = 0;
- DDR_RST |= _BV(RST);
/* /BUSREQ: Output and high */
Z80_O_BUSREQ = 1;
DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
}
+ reset_polarity = Z80_I_RST;
+ z80_reset_active();
+ DDR_RST |= _BV(RST);
+
zstate = RESET;
}
case Reset:
z80_dbus_set_in();
z80_addrbus_set_in();
- Z80_O_RST = 0;
+ z80_reset_active();
Z80_O_BUSREQ = 1;
zstate = RESET;
break;
switch (zstate) {
case RESET:
Z80_O_BUSREQ = 0;
- Z80_O_RST = 1;
+ z80_reset_inactive();
timer = BUS_TO;
while (Z80_I_BUSACK == 1 && timer)
;
z80_addrbus_set_out();
zstate = RESET_AQRD;
} else {
- Z80_O_RST = 0;
+ z80_reset_active();
Z80_O_BUSREQ = 1;
}
break;
case RESET_AQRD:
z80_dbus_set_in();
z80_addrbus_set_in();
- Z80_O_RST = 0;
+ z80_reset_active();
Z80_O_BUSREQ = 1;
zstate = RESET;
break;
case Run:
switch (zstate) {
case RESET:
- Z80_O_RST = 1;
+ z80_reset_inactive();
zstate = RUNNING;
break;